Algorithm and architecture for on-line decimal powering computation

Abstract

An architecture for the computation of a decimal powering function is presented in this paper. The algorithm consists of a sequence of overlapped operations: 1) digit recurrence logarithm, 2) sequential multiplication, and 3) on-line antilogarithm. A correction scheme is introduced between the overlapped operations to guarantee correct on-line calculations. Execution times are estimated for decimal64 and decimal128 formats of the IEEE 754-2008 standard for floating point arithmetic.

Decimal Floating Point Number System

“…Some researchers focused on other functions such as log [69,70], antilog [71], and power [72,73]. Others presented a larger set of elementary functions calculations [74].…”