A DC-offset cancellation circuit for PGA in baseband communication

Abstract

This paper introduces a novel DC-offset cancellation circuit for PGA in baseband communication. The output DC offset is reduced from over one hundred millivolts to less than 4mV in all cases with power dissipation of 6.6,.W. At the same time, spurious-free dynamic range (SFDR) of PGA output is 51.4dB and the settling time of 63dB gain step switching is 372,.s. The chip is fabricated in O.lS,.m CMOS technology.