Review of self tuning methods for direct conversion transceivers

Kladovščikov, Leonid; Navickas, Romualdas

doi:10.1109/estream.2017.7950308

Cited by 1 publication

(2 citation statements)

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“…Firstly, in the master tuning circuit, parasitic capacitance could be induced at the charged node by the comparator or the current source, inducing inherent error. Secondly, as the integrated voltage is compared with a reference voltage, the DC offset in the comparator could also induce considerable error [ 30 , 31 ]. Assume that parasitic capacitance at the charged node C P and offset voltage of the comparator V OFFSET are involved.…”

Section: Conventional Master–slave Tuning Schemementioning

confidence: 99%

“…Since parasitic capacitances could be induced at the charged node, the accuracy of the tuning result could be reduced. Moreover, a comparator is often needed in tuning circuits, but the DC offset of the comparator could induce considerable error [ 30 , 31 ]. The literature shows that a conventional master–slave tuning scheme works well with less critical applications.…”

Section: Introductionmentioning

confidence: 99%

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A High-Accuracy RC Time Constant Auto-Tuning Scheme for Integrated Continuous-Time Filters

Jin,

Wu,

Yin

et al. 2024

Micromachines

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The reliability of the resistor-capacitor (RC) time constant of a continuous-time (CT) filter has long been an obstacle with integrated circuits. Due to process and temperature variations in complementary metal-oxide semiconductor (CMOS) technology, the absolute value of the RC time constant may vary over ±50%, which is a big issue for many integrated continuous-time analog circuits. This study proposes an on-chip RC time constant auto-tuning scheme. The proposed scheme is based on the discrete master–slave auto-tuning concept. Considering the limitations in conventional works, a higher tuning accuracy is achieved by adopting two techniques: firstly, parasitic capacitance cancelation is proposed to eliminate the effects caused by parasitic capacitance; secondly, symmetric comparison is introduced to minimize the influence of the DC offset of the comparator. A successive approximation procedure is applied to improve the tuning speed. The proposed auto-tuning scheme has been validated in 55 nm CMOS technology with a fourth-order active-RC low-pass filter under PVT variations and 60 mV input offset voltage. The average tuning error is 2.21%, and the maximum error is 3.67%. The tuning error of the proposed scheme is considerably lower than the conventional scheme.

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Section: Conventional Master–slave Tuning Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%