A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation

Asaad, Sameh; Bellofatto, R.; Brezzo, Bernard; Haymes, C.; Kapur, Mohit; Parker, B.; Roewer, Thomas; Saha, Proshanta; Takken, Todd; Tierno, J.

doi:10.1145/2145694.2145720

Cited by 60 publications

(13 citation statements)

References 7 publications

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“…From the results presented in Figs. 13,14,15,16,17,18,19, and 20, it can be concluded that mux ratio alone is not a correct indicator of the efficiency of an interconnect topology and in some cases it can be even misleading. So for complete performance picture, it is always better to have the system frequency comparison results for the topologies under consideration.…”

Section: Mux Ratio and Frequency Comparison Resultsmentioning

confidence: 99%

“…The number of FPGAs on the multi-FPGA board normally depends upon the complexity of design under consideration. Their number may vary from a few FPGAs on a single board [14] to several dozen FPGAs on multiple FPGA boards [15]. In multi-FPGA prototyping flow, the quality of inter-FPGA routing interconnect and the capability of corresponding inter-FPGA routing tool to exploit the characteristics of routing interconnect are very vital.…”

Section: Introductionmentioning

confidence: 99%

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Inter-FPGA interconnect topologies exploration for multi-FPGA systems

Farooq

Mehrez

Bhatti

2018

Des Autom Embed Syst

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Prototyping using multi-FPGA systems offers significant advantages over simulation and emulation based pre-silicon verification techniques. Multi-FPGA prototyping follows a complex design flow where the quality of associated tools and the architecture of interconnect topology play a very important role in the performance of final prototyped design. A well designed interconnect topology may remain underutilized because of a poor routing tool and vice versa. This makes the selection of a good routing tool and the exploration of interconnect topologies extremely important for the quality of final design. In this work, we present a detailed comparison between six inter-FPGA interconnect topologies. We present a generic routing tool and for each topology, ten large, complex benchmarks are prototyped on four FPGA boards using this tool. Experimentation reveals that fully customized interconnect topology using a hybrid combination of direct two and multi point tracks gives the best frequency results for all the FPGA boards. On average, this topology gives 26.2, 28.5, 9.5, 32.1 and 12.4% better frequency results as compared to five other interconnect topologies. We also perform routing time comparison and the topology using generic hybrid combination of direct two and multi point tracks gives the best results. On average, this topology produces 1.8×, 2×, 2×, 9.2×, and 4.4× better results as compared to five other topologies under consideration. Frequency-time tradeoff analysis along with flexibility and setup time of different topologies is also performed. It reveals that a partially customized topology with hybrid combination of direct two and multi point tracks gives the best frequency-time tradeoff for smaller FPGA boards while a partially customized topology B Umer Farooq 123 118 U. Farooq et al.with switch-based and multi point connections gives the best results for larger FPGA boards with reasonable flexibility and moderate setup time.

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Section: Mux Ratio and Frequency Comparison Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Inter-FPGA interconnect topologies exploration for multi-FPGA systems

Farooq

Mehrez

Bhatti

2018

Des Autom Embed Syst

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“…Up until this point, we have used the term digitally-driven to refer to analog input signals that change only on digital clock edges, meaning that they are that are piecewise-constant. However, it is possible 1 Relative error is defined as max |y FPGA − y CPU | /max |y CPU |, where y FPGA and y CPU are the FPGA and CPU waveforms, respectively. Figure 11: Amplitude histogram at the DFE output, constructed from emulator data.…”

Section: Handling a Broader Class Of Inputsmentioning

confidence: 99%

“…Top-level simulation is a crucial part of the verification of today's complex chips. For entirely digital designs, FPGA emulation can provide a significant performance boost; gains of 100,000x as compared to CPU simulation have been reported [1]. However, for systems containing mixed-signal components, as most SoCs do today, emulating analog behavior poses a special challenge: not only does one need to create functional models for analog blocks, but those models must be written in a way that can be implemented on an FPGA.…”

Section: Introductionmentioning

confidence: 99%

Fast FPGA emulation of analog dynamics in digitally-driven systems

Herbst

Lim

Horowitz

2018

Proceedings of the International Conference on Computer-Aided Design

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In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog input, and the output is evaluated only when needed by the digital subsystem. Our architecture is therefore intended for digitally-driven systems; that is, those in which the inputs of analog dynamical blocks change only on digital clock edges. We implemented a high-speed link transceiver design using the proposed architecture on a Xilinx FPGA. This design demonstrates how our approach breaks the link between simulation rate and time resolution that is characteristic of prior approaches. The emulator is flexible, allowing for the real-time adjustment of analog dynamics, clock jitter, and various design parameters. We demonstrate that our architecture achieves 1% accuracy while running 3 orders of magnitude faster than a comparable high-performance CPU simulation.

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“…As circuit density increases, so too does the effort required to verify that designs function correctly prior to committing to an expensive fabrication. Traditionally, verifying that the design behaves correctly in a software simulation was sufficient, but with larger and larger circuits, this is no longer the case: IBM reported that the gap between simulation and silicon to be eight orders of magnitude in operating frequency [Asaad et al 2012]. To close this gap, more and more designers are turning to prototyping their designs using field-programmable gate arrays (FPGAs).…”

Section: Introductionmentioning

confidence: 99%

Accelerating FPGA debug

Hung

Wilton

2014

ACM Trans. Des. Autom. Electron. Syst.

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FPGA technology is commonly used to prototype new digital designs before entering fabrication. Whilst these physical prototypes can operate many orders of magnitude faster than through a logic simulator, a fundamental limitation is their lack of on-chip visibility when debugging. To counter this, trace-bufferbased instrumentation can be installed into the prototype, allowing designers to capture a predetermined window of signal data during live operation for offline analysis. However, instead of requiring the designer to recompile their entire circuit every time the window is modified, this article proposes that an overlay network is constructed using only spare FPGA routing multiplexers to connect all circuit signals through to the trace instruments. Thus, during debugging, designers would only need to reconfigure this network instead of finding a new place-and-route solution. Furthermore, we describe how this network can deliver signals to both the trigger and trace units of these instruments, which are implemented simultaneously using dual-port RAMs. Our results show that new network configurations connecting any subset of signals to 80-90% of the available RAM capacity can be computed in less than 70 seconds, for a 100,000 LUT circuit, as many times as necessary. Our tool-QuickTrace-is available for download. ACM Reference Format:Eddie Hung and Steven J. E. Wilton. 2014. Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network.

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A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation

Cited by 60 publications

References 7 publications

Inter-FPGA interconnect topologies exploration for multi-FPGA systems

Inter-FPGA interconnect topologies exploration for multi-FPGA systems

Fast FPGA emulation of analog dynamics in digitally-driven systems

Accelerating FPGA debug

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