A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors

Raghavan, Praveen; Munaga, Satyakiran; Ramos, Estela Rey; Lambrechts, Andy; Jayapala, Murali; Catthoor, Francky; Verkest, D.

doi:10.1007/978-3-540-71270-1_5

Cited by 20 publications

(7 citation statements)

References 9 publications

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“…Previous research has discussed building application specific crossbars for SIMD processors [25]. Such designs hardwired only the swizzle operations needed to support the application, yielding a power efficient design.…”

Section: Swizzle Networkmentioning

confidence: 99%

AnySP: Anytime Anywhere Anyway Signal Processing

et al. 2010

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In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world-a device that we now all depend on in our daily lives. The current generation of devices employs a combination of general-purpose processors, digital signal processors, and hardwired accelerators to provide giga-operations-per-second performance on milliWatt power budgets. Such heterogeneous organizations are inefficient to build and maintain, as well as waste silicon area and power. Looking forward to the next generation of mobile computing, computation requirements will increase by one to three orders of magnitude due to higher data rates, increased complexity algorithms, and greater computation diversity but the power requirements will be just as stringent. Scaling of existing approaches will not suffice instead the inherent computational efficiency, programmability, and adaptability of the hardware must change. To overcome these challenges, this paper proposes an example architecture, referred to as AnySP , for the next generation mobile signal processing. AnySP uses a co-design approach where the next generation wireless signal processing and high-definition video algorithms are analyzed to create a domain specific programmable architecture. At the heart of AnySP is a configurable single-instruction multipledata datapath that is capable of processing wide vectors or multiple narrow vectors simultaneously. In addition, deeper computation subgraphs can be pipelined across the singleinstruction multiple-data lanes. These three operating modes provide high throughput across varying application types. Results show that AnySP is capable of sustaining 4G wireless processing and high-definition video throughput rates, and will approach the 1000 Mops/mW efficiency barrier when scaled to 45nm.

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Section: Swizzle Networkmentioning

confidence: 99%

AnySP: Anytime Anywhere Anyway Signal Processing

et al. 2010

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“…The role of the second pipeline stage (DPU) is to bridge across different SIMD formats. To this end, a crossbar-based DPU similar to [39] is employed to repack words from register R2 or/and R3 into other supported bitwidths. The resulting resized words are then written to register R4 as the input of the first stage (AU) or back to memory.…”

Section: Data Pack Unitmentioning

confidence: 99%

An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs

Yu,

Ponzina,

Levisse

et al. 2024

IEEE Trans. VLSI Syst.

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The ever-increasing computational complexity and energy consumption of today's applications, such as Machine Learning (ML) algorithms, not only strain the capabilities of the underlying hardware but also significantly restrict their wide deployment at the edge. Addressing these challenges, novel architecture solutions are required by leveraging opportunities exposed by algorithms, e.g., robustness to small-bitwidth operand quantization and high intrinsic data-level parallelism. However, traditional Hardware Single Instruction Multiple Data (Hard SIMD) architectures only support a small set of operand bitwidths, limiting performance improvement. To fill the gap, this manuscript introduces a novel pipelined processor microarchitecture for arithmetic computing based on the Softwaredefined SIMD (Soft SIMD) paradigm that can define arbitrary SIMD modes through control instructions at run-time. This microarchitecture is optimized for parallel fine-grained fixedpoint arithmetic, such as shift/add. It can also efficiently execute sequential shift-add-based multiplication over SIMD subwords, thanks to zero-skipping and Canonical Signed Digit (CSD) coding. A lightweight repacking unit allows changing subword bitwidth dynamically. These features are implemented within a tight energy and area budget. An energy consumption model is established through post-synthesis for performance assessment. We select heterogeneously quantized Convolutional Neural Networks (CNNs) from the ML domain as the benchmark and map it onto our microarchitecture. Experimental results showcase that our approach dramatically outperforms traditional Hard SIMD Multiplier-Adder regarding area and energy requirements. In particular, our microarchitecture occupies up to 59.9% less area than a Hard SIMD that supports fewer SIMD bitwidths, while consuming up to 50.1% less energy on average to execute heterogeneously quantized CNNs.

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“…Efficient communication and control flow handling mechanisms are also not supported in the tightly coupled mode. Many previous architectures adopted the SRAM-based shuffle network and the matrix register file Woh (2010), Shahbahrami et al (2008), Raghavan and Munaga (2007). Compared with existing architectures, the main novelties of FT-Matrix's interlane communication structure include the compression of memory space in the SRAM-based shuffle network and the flexible configuration of the multi-grained matrix register file (MMRF).…”

Section: Related Workmentioning

confidence: 99%

Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions

Wang

Liu

et al. 2021

CCF Trans. HPC

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Digital Signal Processors (DSPs) have been widely used in embedded domains, delivering high performance with ultra-low power consumption. Such promises make it attractive for more domains that DSP was not an option before. To show how DSP lives up to these promises, we review two milestone DSPs: FT-Matrix and FT-Matrix2, which are designed by National University of Defense Technology with the purpose of advancing DSPs into the era of higher performance computing, AI, and even beyond. We demonstrate that the key challenges lie in the orchestration of huge computation resources and efficient data supply sub-system design. We show the key mechanisms in both FT-Matrix and FT-Matrix2 targeting these challenges, and also come up with possible future directions for enabling DSPs for a wider scope of applications.

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A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors

Cited by 20 publications

References 9 publications

AnySP: Anytime Anywhere Anyway Signal Processing

AnySP: Anytime Anywhere Anyway Signal Processing

An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs

Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions

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