A Cross-Domain System Architecture for Embedded Hard Real-Time Many-Core Systems

Bradatsch, Christian; Kluge, Florian; Ungerer, Theo

doi:10.1109/hpcc.and.euc.2013.293

Cited by 3 publications

(1 citation statement)

References 13 publications

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“…• The Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability (parMERASA) architecture [79] provides an execution environment for hard real-time applications on a scalable multi-core processor. The parMERASA multi-core processor contains scalable timing analyzable NoCs.…”

Section: Temporal Independencementioning

confidence: 99%

Multi-core Devices for Safety-critical Systems

et al. 2020

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Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

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Section: Temporal Independencementioning

confidence: 99%

Multi-core Devices for Safety-critical Systems

et al. 2020

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Comparison of service call implementations in an AUTOSAR multi-core OS

Bradatsch

Kluge

Ungerer

2014

Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems (SIES 2014)

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Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore

Ungerer

Bradatsch

Frieb

et al. 2016

ACM Trans. Embed. Comput. Syst.

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The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential to parallel program transformation based on parallel design patterns that are timing analyzable. The parallelization approach was applied to parallelize the following industrial hard real-time programs: 3D path planning and stereo navigation algorithms (Honeywell International s.r.o.), control algorithm for a dynamic compaction machine (BAUER Maschinen GmbH), and a diesel engine management system (DENSO AUTOMOTIVE Deutschland GmbH). This article focuses on the parallelization approach, experiences during parallelization with the applications, and quantitative results reached by simulation, by static WCET analysis with the OTAWA tool, and by measurement-based WCET analysis with the RapiTime tool.

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A Cross-Domain System Architecture for Embedded Hard Real-Time Many-Core Systems

Cited by 3 publications

References 13 publications

Multi-core Devices for Safety-critical Systems

Multi-core Devices for Safety-critical Systems

Comparison of service call implementations in an AUTOSAR multi-core OS

Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore

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