A Cost-Efficient L1–L2 Multicore Interconnect: Performance, Power, and Area Considerations

Golander, Amit; Levison, Nadav; Heymann, Omer; Briskman, Alexander; Wolski, Mark J; Robinson, Eric F

doi:10.1109/tcsi.2010.2073832

Cited by 11 publications

(11 citation statements)

References 17 publications

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“…If the total die area is around 400 mm2, then the area overhead for an acceptable latency is around 46.8% for full sharing (nearly half the chip!). For calculating on-chip memory sizes, it is determined to be 1 bit per square micron, or 0.125MB per mm2 for 65 nm technology [2]. If the cache banks were private, and an SBF is used to interconnect these banks to the 8 cores, there would be 3MB of cache memory available for each core.…”

Section: Noc Connecting Shared Cache Memorymentioning

confidence: 99%

“…Where A0 is the wire pitch, W(i) is the i link width (number of wires) and L(i) is the length of link i [2]. Considering 16 bit data signals from one port to another, then, the total area occupied by 24 links that are implemented in 8X metal plane with a wire pitch of 1.6 µm (for 65 nm technology) is estimated to be ~3 mm2 [2].…”

Section: Noc Connecting Shared Cache Memorymentioning

confidence: 99%

“…Therefore, the area required to build the NoC is far smaller than that needed to construct the crossbar. Figure 3 shows the area taken by the crossbar interconnection for 2-way, 4-way, and 8-way sharing for the 8-cores processor [2].…”

Section: Noc Connecting Shared Cache Memorymentioning

confidence: 99%

“…Therefore, This paper addresses the interconnection design issues of area, power and performance of chip multi-processors with shared cache memory. On-chip networks architectures are believed to be the ideal solution for system on chip interconnection problems [2]. Networks on Chip (NoC) can improve design productivity by supporting modularity and reuse of complex cores, thus enabling a higher level of abstraction in architectural modeling of future systems [3].…”

Section: Introductionmentioning

confidence: 99%

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An Efficient Cache Organization for On-Chip Multiprocessor Networks

Awadalla

Sadek

2015

IJECE

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To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes another challenging issue. In most System-on-Chip applications, a shared bus interconnection which needs an arbitration logic to serialize several bus access requests, is adopted to communicate with each integrated processing unit because of its low-cost and simple control characteristics. This paper focuses on the interconnection design issues of area, power and performance of chip multi-processors with shared cache memory. It shows that having shared cache memory contributes to the performance improvement, however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. New interconnection mechanisms are needed to address these issues. This paper proposes an architectural paradigm in an attempt to gain the advantages of having shared cache with the avoidance of penalty imposed by the crossbar interconnect. The proposed architecture achieves smaller area occupation allowing more space to add additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper presents a modified cache coherence algorithm called Tuned-MESI. It is based on the typical MESI cache coherence algorithm however it is tuned and tailored for the suggested architecture. The achieved results of the conducted simulated experiments show that the developed architecture produces less broadcast operations compared to the typical algorithm.

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Section: Noc Connecting Shared Cache Memorymentioning

confidence: 99%

Section: Noc Connecting Shared Cache Memorymentioning

confidence: 99%

Section: Noc Connecting Shared Cache Memorymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Efficient Cache Organization for On-Chip Multiprocessor Networks

Awadalla

Sadek

2015

IJECE

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“…PowerEN offers up to 64 hardware threads per chip and 256 per a 4-way SMP coherent system. It has a unique hierarchical chip multiprocessor (CMP [4]) structure that efficiently shares cache and interconnect resources [5]. A chip has four compute clusters, each compute cluster is constructed of four 64bit PowerPC general-purpose cores that share an L2 cache.…”

Section: A General Purpose Coresmentioning

confidence: 99%

IBM's PowerEN Developer Cloud: Fertile ground for academic research

Golander¹,

Greco²,

Xenidis³

et al. 2010

2010 IEEE 26-Th Convention of Electrical and Electronics Engineers in Israel

Self Cite

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IBM's newest technology, the Power Edge of Network (PowerEN) processor, merges network and server attributes to create a new class of wire-speed processor. PowerEN is a hybrid computer that employs: massive multithreading capabilities, integrated I/O and unique special-purpose accelerators for compression, cryptography, pattern matching, XML and Network processing.As a novel architecture, the PowerEN processor offers fertile ground for research. It can facilitate the development of faster applications in many fields of computer science such as Networking, Cryptography, Virtualization, Bioinformatics, SOA, and Systems. IBM encourages academic research and has set up the "PowerEN Developer Cloud" infrastructure to allow it.

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