A cost-competitive high performance Junction-FET (JFET) in CMOS process for RF &amp;#x00026; analog applications

Shi, Yaning; Rassel, R.; Phelps, R. A.; Candra, Panglijen; Hershberger, D.; Tian, Xiong; Sweeney, S.; Rascoe, J.; Rainey, B.A.; Dunn, J.; Harame, D.L.

doi:10.1109/rfic.2010.5477348

Cited by 9 publications

(7 citation statements)

References 3 publications

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“…The implanted n-channel JFET is a RF feature in IBM's analog and mixed signal technology offering at 180nm node [3]. A cross section is shown in Fig.…”

Section: Ron Optimizationmentioning

confidence: 99%

“…The associated resistance, R series , is determined by the doping in both vertical region from surface to bottom of STI, and the lateral region underneath STI. Since R on scales linearly with the channel length [3], a linear regression is well suited to extract R series from the y-axis intercept. Applying this method to the existing JFET design, the result shows R series accounts for 75% of total R on .…”

Section: Ron Optimizationmentioning

confidence: 99%

“…These features make it a good candidate for RF and analog applications [1] [2], such as low noise amplifier, current source, switch, et al In previous work, we present a low cost JFET integrated in 180nm RFCMOS technology [3]. The device demonstrates the competitive DC, ac, and RF characteristics.…”

Section: Introductionmentioning

confidence: 99%

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Design and optimization of silicon JFET in 180nm RF/BiCMOS technology

Shi

Rassel

Phelps

et al. 2010

2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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in this paper, we discuss a method to extrapolate intrinsic and extrinsic Ron components for a JFET. The results provide the guideline to lower Ron, hence to achieve competitive "Ron vs. pinch off (Voff)" benchmark. The optimization impacts on channel length scaling and process variation are discussed. Besides, an improved RESURF condition is achieved using one of the experimental conditions. The optimized JFET demonstrates the 50% lowered Ron, low Voff of -2.75V, and high BVdss of 11V.

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“…The implanted n-channel JFET is a RF feature in IBM's analog and mixed signal technology offering at 180nm node [3]. A cross section is shown in Fig.…”

Section: Ron Optimizationmentioning

confidence: 99%

Section: Ron Optimizationmentioning

confidence: 99%

See 1 more Smart Citation

Design and optimization of silicon JFET in 180nm RF/BiCMOS technology

Shi

Rassel

Phelps

et al. 2010

2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Often for more aggressive CMOS nodes, only a few implants are available to define JFETs. Additionally, shallow-trench isolation (STI) is used for these JFETs to achieve high breakdown voltages [12]. However, this can compromise flicker noise performance because of charge traps at these STI interfaces.…”

Section: Introductionmentioning

confidence: 99%

CMOS-Integrated Low-Noise Junction Field-Effect Transistors for Bioelectronic Applications

Fleischer

Shekar

Dai

et al. 2018

IEEE Electron Device Lett.

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In this work, we present a CMOS-integrated low-noise junction field-effect transistor (JFET) developed in a standard 0.18 pm CMOS process. These JFETs reduce input-referred flicker noise power by more than a factor of 10 when compared to equally sized n-channel MOS devices by eliminating oxide interfaces in contact with the channel. We show that this improvement in device performance translates into a factor-of-10 reduction in the input-referred noise of integrated CMOS operational amplifiers when JFET devices are used at the input, significant for many applications in bioelectronics.

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“…And it is even more cost-effective to do the integration in standard, commercial technologies without any extra process addition or modification. There have been several attempts to implement JFET's in CMOS and bipolar-CMOS-DMOS (BCD) technologies [1][2][3][4][5][6]. However, these developments required extra implantation steps and/or SOI wafers, and the processes thus developed were all proprietary.…”

Section: Introductionmentioning

confidence: 99%

An input buffer with monolithic JFET in standard BCD technology for sensor applications

Hsu

Chuang

2015

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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A new input buffer with monolithic integrated JFET in standard BCD technologies is presented in this work. The JFET has been implemented without any modification to the standard BCD process. An input buffer with PMOSFET was also fabricated for comparison. Measurements showed that the lowfrequency input referred noise of the JFET input buffer is much smaller than that of the PMOSFET buffer. The proposed circuit can be applied to low-noise front-end amplifiers of sensors.

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A cost-competitive high performance Junction-FET (JFET) in CMOS process for RF & analog applications

Cited by 9 publications

References 3 publications

Design and optimization of silicon JFET in 180nm RF/BiCMOS technology

Design and optimization of silicon JFET in 180nm RF/BiCMOS technology

CMOS-Integrated Low-Noise Junction Field-Effect Transistors for Bioelectronic Applications

An input buffer with monolithic JFET in standard BCD technology for sensor applications

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