A Continuous Time Multi-Bit $\Delta \Sigma$ ADC Using Time Domain Quantizer and Feedback Element

Dhanasekaran, V.; Gambhir, M.; El-Sayed, Mohamed; Sánchez-Sinencio, E.; Silva-Martí­nez, J.; Mishra, C.; Chen, Lei; Pankratz, Erik

doi:10.1109/jssc.2010.2099893

Cited by 52 publications

(26 citation statements)

References 12 publications

(11 reference statements)

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“…The estimation of the TDC/DTC power consumption is given as the digital power of the modulator for comparison purposes. The modulator reported in [8] consumes almost 11 mW for a clock rate as small as 250 MHz.…”

Section: Circuit-level Simulation Resultsmentioning

confidence: 99%

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

Tamaddon

Yavari

2015

Circuit Theory & Apps

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SUMMARYEmbedding the time encoding approach inside the loop of the sigma-delta modulators has been shown as a promising alternative to overcome the resolution problems of analog-to-digital converters in low-voltage complementary metal-oxide semiconductor (CMOS) circuits. In this paper, a wideband noise-transferfunction (NTF)-enhanced time-based continuous-time sigma-delta modulator (TCSDM) with a secondorder noise-coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage-to-time converter and a time-to-digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog-based noise-coupling technique, the modulator's noise-shaping order is improved by two. The concept is elaborated for an NTF-enhanced second-order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit-level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time-based noise-coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced.

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Section: Circuit-level Simulation Resultsmentioning

confidence: 99%

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

Tamaddon

Yavari

2015

Circuit Theory & Apps

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“…The time difference of these two edges determines the pulsewidth to be quantized by the subsequent two-step TDC quantizer. The PWM is composed of voltageto-time converters (VTCs) and a ramp generator (RG) [12], as depicted in Fig. 11(a).…”

Section: Pulsewidth Modulatormentioning

confidence: 99%

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta–Sigma Modulator

Lin

Weng

Wei

et al. 2014

IEEE Trans. Circuits Syst. II

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A time-to-digital converter (TDC)-based two-step quantizer is proposed for a multibit continuous-time delta-sigma modulator (CTDSM). In the proposed time-domain quantizer, the barrel-shifting operation realizes the dynamic element matching (DEM) function inherently, eliminating an explicit DEM circuit and the associated circuit latency. The two-step quantization scheme further reduces the hardware and power consumption of a multibit TDC quantizer. A swapper technique, in addition to the inherent DEM, is incorporated to randomize the selection of the two banks of digital-to-analog converter cells, which ensure good linearity. A third-order CTDSM incorporating the proposed TDC-based two-step quantizer is fabricated in a 90-nm CMOS process. The modulator achieves a signal-to-noise-and-distortion ratio of 69.6 dB over a 1-MHz signal bandwidth. Operated from 1.2-V analog and 1-V digital supplies, the whole CTDSM consumes 1.79 mW and achieves a figure of merit of 361 fJ/conversion. Index Terms-Delta-sigma modulator, inherent dynamic element matching (DEM), time-domain quantizer.

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“…H IGH-PERFORMANCE time-to-digital converters (TDCs) have become increasingly important for all digital phase-locked loops [1], time domain analog-to-digital converters [2], time-of-flight (ToF) measurements [3], [4], and instrumentation applications [5]. It is difficult to achieve all the requirements of low power, high linearity, fine resolution, large dynamic range, and compactness at the same time.…”

Section: Introductionmentioning

confidence: 99%

A Low-Power and Highly Linear 14-bit Parallel Sampling TDC With Power Gating and DEM in 65-nm CMOS

Liu

Zheng

2016

IEEE Trans. VLSI Syst.

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This paper describes time-to-digital converter (TDC) architecture capable of achieving subgate-delay resolution and large detection range at the same time with low power consumption. The proposed TDC is based on a parallel sampling ring oscillator with power gating and dynamic element matching (DEM). Through digital background calibration, the time resolution is determined by the delay difference between successive sampling clocks instead of buffer delay. The ring oscillator is enabled only during the incoming time pulsewidth, leading to low power consumption. A new buffer circuit implementation which enables the ring oscillator to settle to a known position after the ring oscillator stops is proposed. Furthermore, the stop position is latched by cross-coupled inverters to achieve immunity to leakage issues. For each incoming time pulse, the ring oscillator starts oscillation from the buffer before which the previous conversion stops, and thus, it also achieves barrel-shift algorithm for DEM and mitigates buffer mismatch impact. The design is fabricated in 65-nm CMOS technology and occupies a 0.4 mm × 0.3 mm chip area. Measurements of the prototype IC demonstrate a detection range of 98 ns with 6 ps/LSB. It consumes 280 µW from a 1.2 V power supply when operating at a 1-MS/s sampling rate. The measured integral nonlinearity and differential nonlinearity are 0.5 and 0.1 LSB, respectively. Measurements of the prototype IC also demonstrate a single-shot precision of less than 11 ps.

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A Continuous Time Multi-Bit $\Delta \Sigma$ ADC Using Time Domain Quantizer and Feedback Element

Cited by 52 publications

References 12 publications

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta–Sigma Modulator

A Low-Power and Highly Linear 14-bit Parallel Sampling TDC With Power Gating and DEM in 65-nm CMOS

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