A time-to-digital converter (TDC)-based two-step quantizer is proposed for a multibit continuous-time delta-sigma modulator (CTDSM). In the proposed time-domain quantizer, the barrel-shifting operation realizes the dynamic element matching (DEM) function inherently, eliminating an explicit DEM circuit and the associated circuit latency. The two-step quantization scheme further reduces the hardware and power consumption of a multibit TDC quantizer. A swapper technique, in addition to the inherent DEM, is incorporated to randomize the selection of the two banks of digital-to-analog converter cells, which ensure good linearity. A third-order CTDSM incorporating the proposed TDC-based two-step quantizer is fabricated in a 90-nm CMOS process. The modulator achieves a signal-to-noise-and-distortion ratio of 69.6 dB over a 1-MHz signal bandwidth. Operated from 1.2-V analog and 1-V digital supplies, the whole CTDSM consumes 1.79 mW and achieves a figure of merit of 361 fJ/conversion. Index Terms-Delta-sigma modulator, inherent dynamic element matching (DEM), time-domain quantizer.
A 3 rd -order 3-bit continuous-time delta-sigma modulator incorporating several techniques for performance enhancement is presented. In the quantizer, a proposed 3-bit two-step time-domain quantizer is used to facilitate lower power consumption and smaller chip area. In the loop filter, a singleopamp-biquad technique is adopted to realize a 3 rd -order loop filter to reduce the modulator power consumption. With an 8-MHz bandwidth and 256-MHz sampling rate, the measured peak SNDR and dynamic range for this 3 rd -order modulators are 69.6 and 73 dB, respectively. Fabricated in a 90-nm CMOS, the chip consumes 5.01 mW from 1.2-V/1.6-V supply voltages. The FoM is 127 fJ/conversion.
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