A concurrent testing method for NoC switches

Hosseinabady, Mohammad; Banaiyan, A.; Bojnordi, Mahdi Nazm; Navabi, Zainalabedin

doi:10.1109/date.2006.244018

Cited by 35 publications

(12 citation statements)

References 18 publications

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“…It represents that the test cycle of proposed STR is less than the approaches in [3,6,7,10]. Because STR approach supports parallel testing, the test cycle is less than the DfT-based approaches in [6,7,10]. Because our fault model, which described in Sect.…”

Section: Test Cyclementioning

confidence: 96%

“…Hosseinabady et al [6] proposed a wrapper with scan-chains attached to each router on OCNs. One of the routers is defined as a test access switch to receive test patterns from the external test source and broadcast these patterns to other routers.…”

Section: Dft-based Solutionsmentioning

confidence: 99%

“…In order to support aforementioned features, each OCN must embed BISD circuits [5], but BISD-based approach causes a significant area overhead. To overcome this critical area overhead, DfT-based approaches are proposed in [6][7][8][9][10]. However, these approaches suffer from long test cycles while the scale of OCN grows.…”

Section: Introductionmentioning

confidence: 99%

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A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks

Chen

Lin

Shen

et al. 2011

Des Autom Embed Syst

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On-Chip Networks (OCNs) have been proposed to solve the complex on-chip communication problems. In Very Deep-Submicron era, OCN will also be affected by faults in chip due to technologies shrinking. Many researches focused on fault detection and diagnosis in OCN systems. However, these approaches didn't consider faulty OCN system recovery. This paper proposes a scalable built-in self-recovery (BISR) design methodology and corresponding Surrounding Test Ring (STR) architecture for 2D-mesh based OCNs to extend the work of diagnosis. The BISR design methodology consists of STR architecture generation, faulty system recovery, and system correctness maintenance. For an n × n mesh, STR architecture contains one controller and 4n test modules which are formed as a ring-like connection surrounding the OCN. Moreover, these test modules generate test patterns for fault diagnosis during warm-up time. According to these diagnosis results, the faulty system is recovered. Finally, this paper proposes a fault-tolerant routing algorithm, Through-Path Fault-Tolerant (TP-FT) routing, to maintain the correctness of this faulty system. In our experiments, the proposed approach can reduce 68.33∼79.31% unreachable packets and 4.86∼23.6% latency in comparison with traditional approach with 8.48∼13.3% area overhead.

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Section: Test Cyclementioning

confidence: 96%

Section: Dft-based Solutionsmentioning

confidence: 99%

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A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks

Chen

Lin

Shen

et al. 2011

Des Autom Embed Syst

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“…Built-in-self-test (BIST), a well-known approach to diagnose faults, has been extensively addressed as a post-silicon technique for fault detection during the NoC lifetime [4], [20], [11]. To utilize our recovery mechanisms, the network requires to go periodically into selftest in regular intervals and update ISRs and OSRs.…”

Section: Relinoc Architecturementioning

confidence: 99%

ReliNoC: A reliable network for priority-based on-chip communication

Kakoee

Bertacco

Benini

2011

2011 Design, Automation &Amp; Test in Europe

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Abstract-The reliability of networks-on-chip (NoC) is threatened by low yield and device wearout in aggressively scaled technology nodes. We propose ReliNoC, a network-on-chip architecture which can withstand failures, while maintaining not only basic connectivity, but also quality-of-service support based on packet priorities. Our network leverages a dual physical channel switch architecture which removes the control overhead of virtual channels (VCs) and utilizes the inherent redundancy within the 2-channel switch to provide spares for faulty elements. Experimental results show that ReliNoC provides 1.5 to 3 times better network physical connectivity in presence of several faults, and reduces the latency of both high and low priority traffic by 30 to 50%, compared to a traditional VC architecture. Moreover, it can tolerate up to 50 faults within an 8x8 mesh at only 10 and 40% latency overhead on control and data packets for PARSEC traces [24]. Synthesis results show that our reliable architecture incurs only 13% area overhead on the baseline 2-channel switch.

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“…1). Detection can be achieved, for instance, with error correcting codes (ECC) [17] or custom NoC testing mechanisms [18], [19]. Next, the system undergoes diagnosis to determine the fault location.…”

mentioning

confidence: 99%

A Reliable Routing Architecture and Algorithm for NoCs

DeOrio

Fick

Bertacco

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Aggressive transistor scaling continues to drive increasingly complex digital designs. The large number of transistors available today enables the development of chip multiprocessors that include many cores on one die communicating through an on-chip interconnect. As the number of cores increases, scalable communication platforms, such as networks-on-chip (NoCs), have become more popular. However, as the sole communication medium, these interconnects are a single point of failure so that any permanent fault in the NoC can cause the entire system to fail. Compounding the problem, transistors have become increasingly susceptible to wear-out related failures as their critical dimensions shrink. As a result, the on-chip network has become a critically exposed unit that must be protected. To this end, we present Vicis, a fault-tolerant architecture and companion routing protocol that is robust to a large number of permanent failures, allowing communication to continue in the face of permanent transistor failures. Vicis makes use of a two-level approach. First, it attempts to work around errors within a router by leveraging reconfigurable architectural components. Second, when faults within a router disable a link's connectivity, or even an entire router, Vicis reroutes around the faulty node or link with a novel, distributed routing algorithm for meshes and tori. Tolerating permanent faults in both the router components and the reliability hardware itself, Vicis enables graceful performance degradation of networks-on-chip.

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A concurrent testing method for NoC switches

Cited by 35 publications

References 18 publications

A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks

A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks

ReliNoC: A reliable network for priority-based on-chip communication

A Reliable Routing Architecture and Algorithm for NoCs

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