A comprehensive solution for true hierarchical timing and crosstalk delay signoff

Abstract

Leading edge technology advancements have posed big challenges for the digital design flow. Designing multimillion gate ICs at aggressive cycletimes requires new design methodologies and innovative approaches. Hierarchical analysis is a key need to achieve these cycletime goals and gain capacity and runtime advantages in the design flow. Timing and crosstalk delay closure are iterative and hierarchical analysis gains significant cycletime in the overall closure process. In this paper, we present a complete solution for true hierarchical timing and crosstalk delay signoff. The paper discusses challenging problems and caveats with hierarchical signoff and novel solutions to address them. We explore gaps in hierarchical STA and present the first structured solution for hierarchical signoff. The results show 2x-4x cycletime and memory savings using our hierarchical signoff analysis methodology.

A noise and signal integrity verification flow for hierarchical design

“…Block isolation or block shielding is implemented to ensure the blocks are physically bounded and not coupled to the top level nets [1]. Shielding is necessary for all preferred routing layers on each side of the block.…”

“…Although spacing reduce coupling, but it does not entirely eliminate the occurrence of the crosstalk at the edge of the block. Therefore, block shielding comes in handy where the block is shielded for all metal layers [1]. The idea of this research is to come out with signal integrity management and repair methodology to overcome the crosstalk noise in a noisy design.…”

A timing graph based approach to mode merging

“…Request permissions from Permissions@acm.org. DAC'15, June 07 -11, 2015 erarchical timing analysis [3]. While these methods have their own merits and de-merits, they can all benefit from a reduced number of modes achieved by mode merging.…”

Hierarchical Timing Signoff in High Performance ASIC Design

“…Nowadays, as we continue to scale technology with ever shrinking transistor sizes, the amount of logic that can fit to a single chip has increased dramatically. Integrated Circuits have become larger and more complex to provide additional functionality, so it becomes more difficult to perform full chip timing sign-off due to the long run time and large memory requirement.To support this increase in size and complexity, hierarchical timing become a "must have" methodology for most designs [1,2] . In this paper we will describe a new hierarchical flow that significantly reduces the amount of timed logic at the top level, while also allowing for re-use and shelving of macros.…”