Hierarchical design spans the complete framework of a design flow from RTL, synthesis, place and route, timing closure and various other analyses before signoff. Finer geometries and increasing interconnect density however have resulted signal integrity becoming the key issue for Deep SubMicron design. This paper discusses how to analyze, avoid and suggest a proper solution to deal with signal integrity effect in a hierarchical design. The intention is to ensure that a complex design can be delivered to the market with accurate, fast and trusted analysis and sign-off solution. Main proposed approach is to analyze a 45nm process technology hierarchical design using Primetime-SI. Signal integrity effects in the design are explored thoroughly to guarantee any recommendation made to reduce and repair the signal integrity effects is suitable and appropriate. Case study presented demonstrates the proposed methodology has provided valuable and useful perimeter to overcome signal integrity caveats in hierarchical design.
In this paper, an ASIC implementation of a low cost speech recognition system for small vocabulary, 15 isolated word, speaker independent is presented. The IC is a digital block that receives a 12 bit sample with a sampling rate of 11.025 kHz as its input. The IC is running at 10 MHz system clock and targeted at 0.35 µm CMOS process. The whole chip, which includes the speech recognition system core, RAM and ROM contains about 61000 gates. The die size is 1.5 mm x 3mm. The current design had been coded in VHDL for hardware implementation and its functionality is identical with the Matlab simulation. The average speech recognition rate for this IC is 89% for 15 isolated words.
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