A Comprehensive Model for Hot Carrier Degradation in LDMOS Transistors

Moens, P.; Mertens, Johan; Bauwens, F.; Joris, Pierre; Ceuninck, W. De; Tack, M.

doi:10.1109/relphy.2007.369940

Cited by 66 publications

(39 citation statements)

References 8 publications

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“…That means that the ratio of I D and I B is not a suitable measure for the probability that a charge carrier has sufficient energy that it can damage the device. This is in line with the work presented in [33], where it was shown that device degradation is not necessarily correlated to I B for LDMOS devices. To overcome this problem we make use of the expressions derived in [34] for calculating gate currents in standard CMOS.…”

Section: Lucky Electron Modelsupporting

confidence: 92%

“…With the high voltage levels and corresponding electric fields in LDMOS device, however, it can be expected that the lucky electron model may very well be suitable. Unfortunately, in [33], it was already shown that the basic formulation as used in [13] cannot be adopted without adding some empirical fitting functions to describe the V GS dependence. For use in a circuit reliability simulation environment, this approach is not suitable as it is unknown whether these empirical fitting functions can be extrapolated to low V DS .…”

Section: Lucky Electron Modelmentioning

confidence: 99%

See 1 more Smart Citation

Reliability Simulation Models for Hot Carrier Degradation

Scholten

Vries

Bisschop

et al. 2014

Hot Carrier Degradation in Semiconductor Devices

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Because reliability considerations are gradually shifting from device to circuit level (Groeseneken et al., Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies, Proceedings of the ESSDERC, 2010, pp. 64-72), circuit reliability simulation is becoming increasingly important. To enable reliability simulation, reliability simulation models are a prerequisite. These simulation models are often based on analytical descriptions taken from the literature. Apart from the desire to make these models fit experimental data accurately, one encounters some specific practical problems when building them. These problems include (1) the translation from equations derived for DC stress conditions to equations valid under more general transient stress conditions, (2) the translation of the degradation of observables to the degradation of compact model parameters, and (3) the need to keep the simulation overhead of these models to the bare minimum. These issues will be addressed in this chapter, and illustrated using the examples of (1) reverse-V BE degradation in HBTs, (2) hot-carrier degradation in MOSFETs, and (3) hot-carrier degradation in LDMOS devices.

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Section: Lucky Electron Modelsupporting

confidence: 92%

Section: Lucky Electron Modelmentioning

confidence: 99%

Reliability Simulation Models for Hot Carrier Degradation

Scholten

Vries

Bisschop

et al. 2014

Hot Carrier Degradation in Semiconductor Devices

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“…The bulk current and drain current for this electrical stress condition and junction temperature T j = 25°C can be calculated using Eqs. (1) and (5). Using this procedure, the measurement data for V g = 1.5 V were transformed to a junction temperature of T j = 25°C.…”

Section: E-02mentioning

confidence: 99%

“…Due to this manifold of different parameters, it is not straightforward to generally predict the relevant degradation mechanisms during hot carrier stress in advance. Moreover, even for a given device, the relative importance of degradation mechanisms may change with changing stress conditions [5][6][7]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Analysis of hot carrier effects in a 0.35μm high voltage n-channel LDMOS transistor

Enichlmair¹,

Carniello²,

Park³

et al. 2007

Microelectronics Reliability

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“…An overview of the dynamic stress conditions that an LDMOS experiences when switching an inductive load in repetitive clamping mode is given in section II. In section III the parameters of the V D -and V G -dependency of DC-degradation are extracted from experimental data in accordance to [5]. Experimental and simulation results on the hot carrier degradation mechanism are presented in section IV.…”

mentioning

confidence: 99%

Modeling the lifetime of a lateral DMOS transistor in repetitive clamping mode

Riedlberger

Keller

Reisinger

et al. 2010

2010 IEEE International Reliability Physics Symposium

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Hot carrier degradation is critical for LDMOS transistors especially in applications where inductive loads are repetitively switched. In this work, a model for predicting the hot carrier degradation of an LDMOS in dynamic operation conditions is developed and verified for a device driving an inductive load in repetitive clamping mode. Device simulations are performed using the hydrodynamic model. Based on these simulations the physical mechanism of hot carrier degradation is investigated. The results are verified experimentally by photonemission microscopy. Monte-Carlo simulation delivers profound insight into the spatial and energy distribution of the carriers impinging on the Si/SiO 2 -interface.

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A Comprehensive Model for Hot Carrier Degradation in LDMOS Transistors

Cited by 66 publications

References 8 publications

Reliability Simulation Models for Hot Carrier Degradation

Reliability Simulation Models for Hot Carrier Degradation

Analysis of hot carrier effects in a 0.35μm high voltage n-channel LDMOS transistor

Modeling the lifetime of a lateral DMOS transistor in repetitive clamping mode

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