A comprehensive integration infrastructure for embedded system design

Barba, Jesús; Rincón, Fernando; Moya, Francisco; Dondo, Julio; López, Juan Carlos

doi:10.1016/j.micpro.2012.02.007

Cited by 11 publications

(6 citation statements)

References 11 publications

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“…In fact, several UML-based methodologies are also focused on synthesis of HW/SW communications. In [13], a semi-automatic solution for generation of HW/SW infrastructure from UML models is presented. This solution implements a high-level programming interface (software drivers and hardware adapters) using Remote Method Invocation (RMI) semantics as the framework to unify the communication interfaces for all HW and SW components.…”

Section: Innovation With Respect To the State Of The Artmentioning

confidence: 99%

Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics

Posadas

Peñil

Nicolás

et al. 2015

Journal of Systems Architecture

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Section: Innovation With Respect To the State Of The Artmentioning

confidence: 99%

Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics

Posadas

Peñil

Nicolás

et al. 2015

Journal of Systems Architecture

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“…This means an extra cost in terms of communications due to arbitration and transmission cycles. But this overhead is significantly reduced because our platform is based on the principles, tools and infrastructure provided by the OOCE SoC middleware [27]. OOCE allows hardware to hardware transactions by means of special bus wrappers (which are part of the RHC architecture, see Fig.…”

Section: Smart Data Distributionmentioning

confidence: 99%

FPGA acceleration of semantic tree reasoning algorithms

Barba

Santofimia

Dondo

et al. 2015

Journal of Systems Architecture

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“…Several UML-based methodologies also focus on HW/SW communication synthesis. In [22], a semi-automatic solution using Remote Method Invocation (RMI) semantics for generating HW/SW infrastructure from UML models is presented. Similarly, [23] describes a flow to generate code from high-level MARTE for implementation on dynamically reconfigurable SoCs.…”

Section: Evolution Beyond the State Of The Artmentioning

confidence: 99%

Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project

Posadas¹,

Nicolás²,

Peñil³

et al. 2014

Microprocessors and Microsystems

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In this article, we present the work-in-progress of the EU FP7 PHARAON project, started in September 2011. The first objective of the project is the development of new techniques and tools capable to guide and assist the designer in the development process, from UML specifications to implementation and debug on multicore platform. This tool chain will offer the possibility to propose and implement several parallelization strategies and drive the designer into implementation steps. The second objective of the project is to develop monitoring and control techniques in the middleware of the system capable to automatically adapt platform services to applications requirements and therefore reduce power consumption in a transparent manner for applications. embedded systems to integrate a growing range of complex functionalities. A smart phone, for example, is capable to communicate through 3G and WIFI connections while running other applications on Android or Windows Phone. It integrates phone services with high performance graphics and sophisticated software applications such as real-time video and audio. Designers are facing challenging problems as hardware architectures are evolving faster than multicore software development techniques. These techniques are not yet capable to provide efficient methodologies to exploit the full potential of multicore architectures satisfying all the requirements of embedded systems, including performance and power consumption. Accurately predicting the performance of an application implemented on such architectures has become very difficult, because of numerous factors such as cache coherency. Moreover, commonly taught programming models, that are generally based on sequential languages, are no longer sufficient, since early consideration of parallelism in applications has become critical. The lack of efficient software design techniques increases both software development costs and implementation risk in terms of costs and delays. Parallelism, heterogeneity, complex memory structures, efficient power monitors and controllers, are among the list of new functionalities provided by recent multicore systems that require to be adequately tackled by new design ⇑ Corresponding author.

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A comprehensive integration infrastructure for embedded system design

Cited by 11 publications

References 11 publications

Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics

Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics

FPGA acceleration of semantic tree reasoning algorithms

Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project

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