A comprehensive high-level synthesis system for control-flow intensive behaviors

Wang, W.; Tan, Tat Kee; Luo, Jiong; Fei, Yunsi; Shang, Li; Vallerio, Keith S.; Lin, Zhouchen; Raghunathan, Anand; Jha, Niraj K.

doi:10.1145/764808.764812

Cited by 20 publications

(13 citation statements)

References 9 publications

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“…Typical HLS tasks such as scheduling, resource allocation, module binding, module selection, register binding and clock selection are executed simultaneously in [13] so as to achieve better optimization in design energy, power and area. The scheduling algorithm utilized in [13] applies concurrent loop optimization and multi cycling and it is driven by resource constraints.…”

Section: Related Workmentioning

confidence: 99%

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Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Dossis¹

2017

IRATJ

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Design environments and automated CAD systems are proliferated nowadays with various preferences and restrictions in their work environments. One serious problem of automated high-level synthesis tools is their inability of at least difficulty to use for low, bit level functions such as signal processing blocks. Here the Cubed-C environment is used for the rapid implementation of a number of low level functions and blocks such as UARTs without difficulty. Cubed-C is a full-strength high-level synthesis CAD system; nevertheless, its structure and properties make it particularly suitable for this type of fine-grained applications. The experiments in this paper prove that the Cubed-C synthesis tools are particularly suitable for both complex and for low, bit level signal coding functions.

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Section: Related Workmentioning

confidence: 99%

“…The scheduling algorithm utilized in [13] applies concurrent loop optimization and multi cycling and it is driven by resource constraints. The tool generates RTL Verlog implementations.…”

Section: Related Workmentioning

confidence: 99%

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Dossis¹

2017

IRATJ

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“…The front-ends exchange information with the back-ends using intermediate formats, such as the Electronic Design Interchange Format (EDIF) [9,10], used by most E-CAD tools. Complex control flow optimization has been evaluated in [2,11,12], but for small parts of code and by no means complete application tests [13], discusses synthesis for distributed logic and memory [14] uses communicating processes as a system specification medium. HLS methods that include memory access management are outlined in [1], where digital signal processing (DSP) and streaming applications are synthesized using performance constraints [15], analyses mutually exclusive scheduling on extended data-flow graphs (EDFG) [16] synthesizes behavioural descriptions with time constraints, where complex operations are decomposed into simpler ones, and a similar set of decomposed fragments of operators, with the same pattern, are scheduled in a clock cycle.…”

Section: Existing Work In Intelligent Hls Techniquesmentioning

confidence: 99%

Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques

Dossis¹

2013

Adv Robot Autom

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The advancing complexity of contemporary microelectronics has motivated research in high-level and system synthesis (HLS). Formal and intelligent HLS techniques are presented in this contribution, thus the generated implementation is correct-by-construction. These intelligent techniques include RDF (Resource Description Framework) and logic relations, along with automatic implementation options and they are employed for the transformations of a hardware compiler. The proposed toolset utilizes compiler-generators, RDF rules and logic programming in combination with XML validation of the internal state of the compiler. These intelligent and formal techniques make the whole transformation from source code to implementation, formal. The HLS tool is enhanced with the Parallel, Abstract Resource -Constrained Scheduler, which aggressively optimizes the initial state schedules, into maximally parallelized ones. A number of custom options are applied by the user of this toolset, in order to automatically compile selected testcases from real-world applications which prove the usability of the embedded scheduler and the formal compilation of the intelligent HLS compiler. Synthesis of Custom Hardware from ADA with Artificial Intelligence TechniquesMichael Dossis* In [17] an actor, that is used to model every module or system process, communicates with other actors via communication channels. These actors are used by the System Co-Designer [17] to exercise electronic system level (ESL) design space exploration. In [18] the SURYA system utilises the Simplify theorem prover to prove that the RTL model generated by HLS tools is functionally-equivalent to the specification. SURYA found two bugs in the SPARK HLS tool [2], which were until then unknown. In [19] flip-flops are replaced with latches so as to improve implementation timing, since latches are inherently more tolerant to process variations than flip-flops. Nevertheless, latchbased design is more cumbersome than flip-flops. The W3C Resource Description FrameworkThe Resource Description Framework (RDF) is a metadata model and is used to model the information of web resources [7]. RDF models include subject-predicate-object relations with explicit statements, called triplets. Triplets specify resources that store knowledge, information and data retrieval in large automated software tools. This is achieved due to the suitability of RDF to capture, store, exchange, and use machine-readable web information. Here, RDF is used to formally model and validate the internal data and state of the author's HLS tool.The eXtensible Markup Language (XML) serialization format is used to define RDF. XML's syntax is formally specified [7] and is ideal to model simple triples such as subject-predicate-object (and other) relations. The following RDF relation: High-level Synthesis

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“…A recent study by Stitt et al [16] shows how words recently read from memory can be reused. 3) Access ordering and access scheduling: A huge body of work in HLS systems addresses the problem of static scheduling in memory-intensive applications [5], [6], [17]- [19]. Most of these efforts start with a control dataflow-graph specification, where memory references are explicitly marked (i.e., statically disambiguated).…”

Section: A Specification Supportmentioning

confidence: 99%

“…Although some HLS tools allow some type of memory abstraction, they all impose heavy restrictions on the use of these abstractions. For example, many HLS tools impose a fixed access latency for memory accesses [3], [5], [6]. This is usually the worst case (and often unacceptable) latency for a memory access, and, in general, all of the tools restrict the input specification to statically explicit memory dependences.…”

mentioning

confidence: 99%

Hardware compilation of application-specific memory-access interconnect

Venkataramani

Bjerregaard

Chelcea

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integrated circuit systems is the presence of memory accesses to a shared-memory subsystem. The latency to access memory is often not statically predictable, which creates problems for scheduling operations dependent on memory reads. More fundamental is that dependences between accesses may not be statically provable (e.g., if the specification language permits pointers), which introduces memory-consistency problems. Addressing these issues with static scheduling results in overly conservative circuits, and thus, most state-of-the-art HLS tools limit memory systems to those that have predictable latencies and limit programmers to specifications that forbid arbitrary memory-reference patterns. A new HLS framework for the synthesis and optimization of memory accesses (SOMA) is presented. SOMA enables specifications to include arbitrary memory references (e.g., pointers) and allows the memory system to incorporate features that might cause the latency of a memory access to vary dynamically. This results in raising the level of abstraction in the input specification, enabling faster design times. SOMA synthesizes a memory access network (MAN) architecture that facilitates dynamic scheduling and ordering of memory accesses. The paper describes a basic MAN construction technique that illustrates how dynamic ordering helps in efficiently maintaining memory consistency and how dynamic scheduling helps alleviate the variable-latency problem. Then, it is shown how static analysis of the access patterns can be used to optimize the MAN. One optimization changes the MAN interconnect topology to increase concurrence. A second optimization reduces the synchronization overhead necessary to maintain memory consistency. Postlayout experiments demonstrate that SOMA's application-specific MAN construction significantly improves power and performance for a range of benchmarks.Index Terms-Communication synthesis, dataflow synthesis, high-level synthesis (HLS), interface design.

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A comprehensive high-level synthesis system for control-flow intensive behaviors

Cited by 20 publications

References 9 publications

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques

Hardware compilation of application-specific memory-access interconnect

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