A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM

Nair, Sarath Mohanachandran; Bishnoi, Rajendra; Tahoori, Mehdi B.

doi:10.1109/tvlsi.2019.2904197

Cited by 10 publications

(4 citation statements)

References 35 publications

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“…affected by variations due to the combined effect of these two processes. Permanent faults in MRAM can be caused by extreme parametric variations, as described in [43] and [44]. These variations come from changes in both material and lithographic properties, transistor electrical properties, and noise generated by thermal effects [41], [42].…”

Section: ) Strong or Weak Defectsmentioning

confidence: 99%

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

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| Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed Manuscript

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Section: ) Strong or Weak Defectsmentioning

confidence: 99%

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

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“…Overall design and reliability analysis framework used in this project is depicted in In this project, we have developed model for both reliability failures such as read/write failures, read-disturb and retention failures as well as permanent faults due to parametric variations of the STT-MRAM. The yield analysis flow is presented in detail in [10]. The parameters considered in our analysis are the radius (r) of the MTJ and the threshold voltage (V th ) of all CMOS components.…”

Section: Frameworkmentioning

confidence: 99%

“…Fig.5: Percentage of chips with their fault types for a 512×512 memory at 25 • C for various correlation coefficients (φ)[10].…”

mentioning

confidence: 99%

A Universal Spintronic Technology based on Multifunctional Standardized Stack

Tahoori¹,

Nair²,

Bishnoi³

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

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“…MRAM scanning is much faster than DRAM and SRAM. MRAM shows poor writing performance but is hidden in FPGAs [14]. When FPGAs are used as accelerators, LUT only performs memory scanning functions to scan the associated logic.…”

Section: Introductionmentioning

confidence: 99%

An optimal design modeling of non-volatile dynamical reconfigurable FPGA using SOT-MRAM for ultra-low power applications

Hussain¹,

Reddy²,

Kishore³

2022

Preprint

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The rapid development of reconfigurable FPGA circuits will facilitate their use and operation at low cost. The design of internal memory of FPGA circuit controls their future development. Spin RAM and Magnetic RAM (MRAM) are the best solutions for FPGA for reducing power and writing time. In terms of memory technology, MRAM is becoming more and more attractive in the industry due to its promising capabilities. The physical design range still causes significant radiation effects such as write error rate, access time, tunnel breakage, and low MRAM power consumption. However, random MRAM writing processes affect their yield, so process variations should be investigated, which increases the complexity of yield analysis. For further enhancement of non-volatile FPGA circuits, we propose an optimal design modeling of non-volatile dynamical reconfigurable FPGA using SOT-MRAM for ultra-low power applications. We first introduce a spin-orbit torque-based MRAM (SOT-MRAM), which significantly reduces exposure to radiation caused by offline reading and writing. We design SOT-MRAM based on a double barrier magnetic tunnel connector (DMTJ) with two reference layers to ensure high power and right length. After that, we develop an optimal SOT-MRAM design using the butterfly induced sunflower optimization (BSFO) algorithm which optimizes the design parameters of writing processes. Finally, the simulation results of proposed design can be compared with the existing state-of-art designs in terms of different simulation metrics.

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A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM

Cited by 10 publications

References 35 publications

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

A Universal Spintronic Technology based on Multifunctional Standardized Stack

An optimal design modeling of non-volatile dynamical reconfigurable FPGA using SOT-MRAM for ultra-low power applications

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