A Comprehensive Evaluation of Functional Programs for Power-Aware Test

Touati, A.; Bosio, Alberto; Dilillo, Luigi; Girard, Patrick; Todri‐Sanial, Aida; Virazel, Arnaud; Bernardi, P.

doi:10.1109/natw.2014.23

Cited by 2 publications

(1 citation statement)

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“…The latter is also reduced thanks to a static compaction algorithm. Finally, in [9], authors present an analysis of functional test programs from the verification and test point of view.…”

Section: Introductionmentioning

confidence: 99%

STT MRAM-Based PUFs

Vatajelu

Natale

Indaco

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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High power consumption during at-speed delay fault testing may lead to yield loss and premature aging. On the other hand, reducing too much test power might lead to test escape and reliability problems. Thus, to avoid these issues, test power has to map the power consumed during functional mode. Existing works target the generation of functional test programs able to maximize the power consumption in functional mode of microprocessor cores. The obtained power consumption will be used as threshold to tune the power consumed during testing. This paper investigates the impact of re-using such functional test programs for testing purposes. We propose to apply them by exploiting existing DfT architecture to maximize the delay fault coverage. Then, we combine them with the classical at-speed LOC and LOS delay fault testing schemes to further increase the fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage while respecting the functional power budget.

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“…The latter is also reduced thanks to a static compaction algorithm. Finally, in [9], authors present an analysis of functional test programs from the verification and test point of view.…”

Section: Introductionmentioning

confidence: 99%