A complete model of E/sup 2/PROM memory cells for circuit simulations

Pavan, Paolo; Larcher, Luca; Cuozzo, M.; Zuliani, P.; Conte, A.

doi:10.1109/tcad.2003.814952

Cited by 14 publications

(3 citation statements)

References 14 publications

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“…11) The proposed circuit-level macro model in this work simply consists of one transistor, one capacitor, and one voltage-controlled current source (VCCS) where the transient behaviors are mathematically embedded, with the improved compactness by reducing the number of current sources in the previous works. [12][13][14][15][16] For expecting higher credibility of the developed SPICE models, they are verified by the measurement results from the fabricated CTF memory devices having the silicon-oxide-nitride-oxide-silicon (SONOS) stack under various operating conditions, by which plausible agreements between modeling and measurement results are demonstrated. Our more realistic circuit-level macro model would be practical and beneficial in designing the high-density 2D and 3D memory array and system architectures for 3D CTF memory.…”

Section: Introductionmentioning

confidence: 65%

Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

Kim

Lee

Kim³

et al. 2016

Jpn. J. Appl. Phys.

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In this paper, a highly reliable circuit model of gate-all-around (GAA) charge-trap flash (CTF) memory cell is proposed, considering the transient behaviors for describing the program operations with improved accuracy. Although several compact models have been reported in the previous literature, time-dependent behaviors have not been precisely reflected and the failures tend to get worse as the operation time elapses. Furthermore, the developed SPICE models in this work have been verified by the measurement results of the fabricated flash memory cells having silicon–oxide–nitride–oxide–silicon (SONOS). This more realistic model would be beneficial in designing the system architectures and setting up the operation schemes for the leading three-dimensional (3D) stack CTF memory.

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Section: Introductionmentioning

confidence: 65%

Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

Kim

Lee

Kim³

et al. 2016

Jpn. J. Appl. Phys.

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“…Its voltage is controlled through capacitive coupling with the external nodes of the device. Often, the floating-gate transistor is modelled by a capacitor equivalent circuit called the capacitor model [10]. In practice, write/erase characteristics for many EEPROM/Flash memories are close to that of a charge/ discharge of a capacitor.…”

Section: Experimental Methodsmentioning

confidence: 99%

Data Remanence in Flash Memory Devices

Skorobogatov

2005

Cryptographic Hardware and Embedded Systems – CHES 2005

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Abstract. Data remanence is the residual physical representation of data that has been erased or overwritten. In non-volatile programmable devices, such as UV EPROM, EEPROM or Flash, bits are stored as charge in the floating gate of a transistor. After each erase operation, some of this charge remains. Security protection in microcontrollers and smartcards with EEPROM/Flash memories is based on the assumption that information from the memory disappears completely after erasing. While microcontroller manufacturers successfully hardened already their designs against a range of attacks, they still have a common problem with data remanence in floating-gate transistors. Even after an erase operation, the transistor does not return fully to its initial state, thereby allowing the attacker to distinguish between previously programmed and not programmed transistors, and thus restore information from erased memory. The research in this direction is summarised here and it is shown how much information can be extracted from some microcontrollers after their memory has been 'erased'.

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“…Compact models implemented in SPICE have been extensively used for IC development. However, to ensure accuracy and predictivity, the models should be physically formulated as functions of both the fundamental process parameters that control device electrical behavior and geometric layout parameters associated with a device as in [1]. Such requirement is very challenging for RRAM modeling, as its operation mechanism is an electrochemical redox process.…”

Section: Introductionmentioning

confidence: 99%

A Predictive Compact Model of Bipolar RRAM Cells for Circuit Simulations

Chiang

Hsu²,

Ding

et al. 2015

IEEE Trans. Electron Devices

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A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. Index Terms-Bipolar switching, compact model, resistive random access memory (RRAM).

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A complete model of E/sup 2/PROM memory cells for circuit simulations

Cited by 14 publications

References 14 publications

Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

Data Remanence in Flash Memory Devices

A Predictive Compact Model of Bipolar RRAM Cells for Circuit Simulations

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