A compiler that easily retargets high level language programs for different signal processing architectures

Abstract

This paper describes a compiler for signal processing applications with high level language control structures and the ability to express computational parallelism. There are two expert system back ends that generate code using advice about the architecture of the target machine(s). The first back end generates code for control flow, and the second generates code for computation. Both expert systems use a rule base that describe the number, type, and architecture of the target processors. If an instruction cannot be directly implemented, then functionally equivalent intermediate language statements are automatically generated. Currently, the prototype compiler generates TMS320 family assembly code and code for distributed memory parallel computers.