A comparison of high-efficiency UHF RFID rectifiers using internal voltage compensation and zero-threshold-voltage MOSFETs

Matias, M. L.; Cunha, J. P. C.; Fabbro, Paulo Augusto Dal; Mioni, D.; Prodanov, William; Pessatti, Murilo Pilon; Leite, Bernardo; Mariano, André

doi:10.1109/lascas.2014.6820301

Cited by 11 publications

(6 citation statements)

References 9 publications

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“…First, the use of zero-Vth transistors [5,16] but this will increase power conversion efficiency at a cost of high reverse/OFFstate leakage current. Second approach is the use of auxiliary voltage source to compensate part (b), which is as shown follows,…”

Section: Proposed Cascading Schemementioning

confidence: 99%

“…where V aux is the auxiliary voltage source that can be obtained either externally [7] or internally [16]. Figure 4 shows the schematic of the proposed signaling scheme to develop the auxiliary voltage V aux by using the input RF signal.…”

Section: Proposed Cascading Schemementioning

confidence: 99%

“…Similarly, the voltage developed across C s1 during the discharging phase can be obtained by substituting (15) in (16). The resultant equation for this voltage (V cs1 ) is shown in (17).…”

Section: Proposed Cascading Schemementioning

confidence: 99%

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A novel cascading scheme to improve the performance of voltage multiplier circuits

Chouhan

Halonen

2015

Analog Integr Circ Sig Process

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The voltage multiplier (VM) circuit is a cascade arrangement designed from a series of rectifiers to obtain high DC output voltage. In this classical approach, the DC voltage which is getting generated in the present stage contributes to the next stage. This phenomenon is recurring at every stage resulting into higher DC output voltage than previous. The proposed signaling scheme enables the use of the rectified DC voltage/stage in a classical way along with the involvement of instantaneous input RF voltage. As a result, higher output DC voltage and improved power conversion efficiency (PCE) will be achieved as compared to a conventional VM circuit signaling scheme. The conventional VM circuit used in this work was designed by stacked series arrangement of three standard differential drive rectifiers. Similarly, the proposed VM circuit was formed by implementing proposed signaling scheme into the conventional VM circuit. These architectures were implemented in a standard 0.18 lm CMOS technology The measurements were done by using input RF signal frequency of 433 MHz for resistive load values of 30, 100 KX, and 1 MX respectively. The measured results show that the proposed VM scheme has 22-32 % better power conversion efficiency than the conventional VM scheme.

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Section: Proposed Cascading Schemementioning

confidence: 99%

Section: Proposed Cascading Schemementioning

confidence: 99%

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A novel cascading scheme to improve the performance of voltage multiplier circuits

Chouhan

Halonen

2015

Analog Integr Circ Sig Process

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“…An Ultra High Frequency (UHF) rectification unit based on voltage doubler is also designed with the technique of internal voltage cancellation to facilitate a zero-threshold transistor. They have claimed to achieve a good with reduced area [5]. A very widely used structure in EH is the Dickson charge pump.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a Modified TG Rectifier with Substrate Voltage Compensation Techniques at 45 nm Technology for High Frequency Low Power RF Energy Harvesting

Sarma

2020

Wseas Transactions on Electronics

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- The development of latest generation of wireless communication standards in the recent years has created enormous possibility to deploy high speed wireless network throughout the globe. There is always demand for high speed, seamless data connectivity. But it is a well-known fact that the increase in speed always makes the power consumption higher. Also while attempting to cater to the need of connectivity to a remote location, the major bottleneck is the availability of power. Hence incorporating self-sustainability to a wireless network is becoming the need of the hour. Radio frequency (RF) energy harvesting (EH) is gaining much attention in contemporary communications in this context. In the design of an EH system, the high frequency rectifier plays a significant role. Apart from several design hurdles that exist in a high frequency rectifier, to attain a high percentage conversion efficiency (PCE) at lower input power is the primary design challenge. This paper presents a design of a modified transmission gate (TG) based high frequency rectifier with two substrate voltage compensation techniques, viz. capacitor and MOS based compensation for RF EH system.The proposed capacitor and MOS based techniques enable the rectifier to achieve a PCE upto 86% and 92% at -5dBm respectively in its single stage implementation. This can be claimed to be the highest in-class efficiency as compared to recently published works. The frequency responses with both the techniques depict a wide band performance covering all popular wireless bands. The dynamic power dissipations (DPD) observed are 12nW and 16nW at -5dB, whereas the leakage power (LP) is 20x10-51W and zero respectively. Further such an performance are obtained using minimal number of transistors, viz. 4 and 5 respectively.

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“…In device based method, rectifiers are implemented by using Schottky diodes [11], zero-threshold transistors [12] and native transistors [13]. These implementations require dedicated manufacturing steps.…”

Section: Introductionmentioning

confidence: 99%

A complete analysis and measurement results of the threshold voltage cancellation scheme for RF to DC converter

Chouhan

Halonen

2015

Analog Integr Circ Sig Process

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In this work, the threshold voltage cancellation scheme for the RF-to-DC converter used in RF energy harvesting is presented. The proposed scheme reduces the threshold voltage of PMOS transistor used in CMOS rectifier with the use of additional CMOS components. The performance of the proposed scheme is evaluated against the conventional CMOS rectifier in terms of the power conversion efficiency (PCE). Measurements were done at 433 MHz RF frequency for resistive load values ranging from 1 to 120 KX. The measured peak PCE of the conventional CMOS and proposed rectifiers are 16 and 35 %, respectively, for the input RF power level of À8 dBm and resistive load of value 10 KX. The implementation of the proposed scheme is also tested in the multi-stage rectifier circuit (MSC) topology. All PMOS-based DTMOS-biased MSC circuit was selected to implement the proposed scheme and for performance comparison. The measured results show the PCE of a five stage DTMOS-biased MSC circuit is 15 % @ À6 dBm with 66 KX resistive load whereas after implementing proposed scheme on the alternate PMOS transistors of DTMOS-biased MSC circuit resulted into 19 % PCE for the same input and output conditions.

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A comparison of high-efficiency UHF RFID rectifiers using internal voltage compensation and zero-threshold-voltage MOSFETs

Cited by 11 publications

References 9 publications

A novel cascading scheme to improve the performance of voltage multiplier circuits

A novel cascading scheme to improve the performance of voltage multiplier circuits

Design and Analysis of a Modified TG Rectifier with Substrate Voltage Compensation Techniques at 45 nm Technology for High Frequency Low Power RF Energy Harvesting

A complete analysis and measurement results of the threshold voltage cancellation scheme for RF to DC converter

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