A comparison of embedded reconfigurable video-processing architectures

Claus, Christopher; Stechele, Walter; Kovatsch, Matthias; Angermeier, Josef; Teich, Jürgen

doi:10.1109/fpl.2008.4630015

Cited by 15 publications

(7 citation statements)

References 6 publications

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“…Recent work in partial reconfiguration of FPGAs provides insight into the stateof-the-art. Claus et al [10] give a comparison of embedded reconfigurable videoprocessing architectures. They propose a hybrid of two hardware platforms: one providing easy reconfiguration of modules and the other providing easy implementation with higher clock frequency, to achieve an optimal FPGA-based dynamically and partially reconfigurable platform for real-time video and image processing.…”

Section: Background and Related Workmentioning

confidence: 99%

Polymorphic Wavelet Transform

Pande

Zambreno

2013

Embedded Multimedia Security Systems

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Many modern computing applications have been enabled through the use of real-time multimedia processing. While several hardware architectures have been proposed in the research literature to support such primitives, these fail to address applications whose performance and resource requirements have a dynamic aspect. Embedded multimedia systems typically need a power and computation efficient design in addition to good compression performance. In this chapter, we introduce a Polymorphic Wavelet Architecture (Poly-DWT) as a crucial building block towards the development of embedded systems to address such challenges. We illustrate how our Poly-DWT architecture can potentially make dynamic resource allocation decisions, such as the internal bit representation and the processing kernel, according to the application requirements. We introduce a filter switching architecture that allows for dynamic switching between 5/3 and 9/7 wavelet filters and leads to a more power-efficient design. Further, a multiplier-free design with a low adder requirement demonstrates the potential of Poly-DWT for embedded systems. Through an FPGA prototype, we perform a quantitative analysis of our Poly-DWT architecture, and compare our filter to existing approaches to illustrate the area and performance benefits inherent in our approach. Poly-DWT serves as an example of joint design of algorithms and architectures for multimedia compression.

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Section: Background and Related Workmentioning

confidence: 99%

Polymorphic Wavelet Transform

Pande

Zambreno

2013

Embedded Multimedia Security Systems

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“…Recent works in partial reconfiguration of FPGAs implement DWT in a reconfigurable fashion. Claus et al (2008) gives a comparison of embedded reconfigurable video-processing architectures. They propose a hybrid of two hardware platforms: one providing easy reconfiguration of modules and the other providing easy implementation with higher clock frequency, to achieve an optimal FPGA-based dynamically and partially reconfigurable platform for real-time video and image processing.…”

Section: Reconfigurable Hardware Implementationmentioning

confidence: 99%

Reconfigurable hardware implementation of a modified chaotic filter bank scheme

Pande

Zambreno

2010

IJES

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Chaotic filter bank schemes have been proposed in the research literature to allow for the efficient encryption of data for real-time embedded systems. Some security flaws have been found in the underlying approaches which makes such a scheme unsafe for application in real life scenarios. In this paper, we first present an improved scheme to alleviate the weaknesses of the chaotic filter bank scheme, and add enhanced security features, to form a modified chaotic filter bank (MCFB) scheme. Next, we present a reconfigurable hardware implementation of the MCFB scheme. Implementation on reconfigurable hardware speeds up the performance of MCFB scheme by mapping some of the multipliers in design to reconfigurable look-up tables, while removing many unnecessary multipliers. An optimised implementation on Xilinx Virtex-5 XC5VLX330 FPGA gave a speedup of 30% over non-optimised direct implementation. A clock frequency of 88 MHz was obtained.

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“…DPR has been used for streaming vision processing [3], [4] at a coarse time-scale, where the time between reconfigurations is within seconds to minutes range, to repurpose the FPGA for different functionalities. In [11], the authors identified the issues of asynchronous module execution and frame skipping when applying DPR for repurposing in a vision streaming context. Streaming Vision Pipeline.…”

Section: Introductionmentioning

confidence: 99%

Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration

Nguyen

Hoe

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by multiple realtime computer vision pipelines. The presented time-sharing runtime framework manages an FPGA fabric that can be roundrobin time-shared by different pipelines at the time scale of individual frames. In this new use-case, the challenge is to achieve useful performance despite high reconfiguration time. The paper describes the basic runtime support as well as four optimizations necessary to achieve realtime performance given the limitations of DPR on today's FPGAs. The paper provides a characterization of a working runtime framework prototype on a Xilinx ZC706 development board. The paper also reports the performance of realtime computer vision pipelines when time-shared.

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A comparison of embedded reconfigurable video-processing architectures

Cited by 15 publications

References 6 publications

Polymorphic Wavelet Transform

Polymorphic Wavelet Transform

Reconfigurable hardware implementation of a modified chaotic filter bank scheme

Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration

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