Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration

Nguyen, Marie; Hoe, James C.

doi:10.1109/fpl.2018.00046

Cited by 8 publications

(3 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…In a PR-style design, the designer decides how the FPGA is divided into PR regions and when/which reconfigurations are needed during the design's execution. For instance, in [22], to accelerate a vision processing pipeline, a PR region is reconfigured every few milliseconds with different pipeline stages.…”

Section: Background and Related Workmentioning

confidence: 99%

Partial Reconfiguration for Design Optimization

Nguyen

Serafin

Hoe

2020

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

Self Cite

View full text Add to dashboard Cite

FPGA designers have traditionally shared a similar design methodology with ASIC designers. Most notably, at design time, FPGA designers commit to a fixed allocation of logic resources to modules in a design. At runtime, some of the occupied resources could be left idle or under-utilized due to hard-toavoid sources of inefficiencies (e.g., operation dependencies). With partial reconfiguration (PR), FPGA resources can be re-allocated over time. Therefore, using PR, a designer can attempt to reduce idleness and under-utilization with better area-time scheduling.In this paper, we explain when, how, and why PR-style designs can improve over the performance-area Pareto front of ASICstyle designs (without PR). We first introduce the concept of area-time volume to explain why PR-style designs can improve upon ASIC-style designs. We identify resource under-utilization as an opportunity that can be exploited by PR-style designs. We then present a first-order analytical model to help a designer decide if a PR-style design can be beneficial. When it is the case, the model points to the most suitable PR execution strategy and provides an estimate of the improvement. The model is validated in three case studies.

show abstract

Section: Background and Related Workmentioning

confidence: 99%

Partial Reconfiguration for Design Optimization

Nguyen

Serafin

Hoe

2020

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

Self Cite

View full text Add to dashboard Cite

show abstract

“…A variation of this work was proposed in [32] for overlays running in cloud accelerators. Real-time video pipelines can also benefit from this type of reconfiguration, as shown in [33]. The aforementioned applications used a reconfiguration style that can be considered as medium grain, with only a few RRs connected to each other through the static system.…”

Section: B Medium Granularitymentioning

confidence: 99%

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

et al. 2020

View full text Add to dashboard Cite

Dynamic partial reconfiguration technique can be used to modify regions of an FPGA as large as the whole reconfigurable fabric or as small as individual logic elements. However, FPGA manufacturers have focused their efforts on designing tools that support the design of monolithic reconfigurable accelerators spanning large regions of the device. Nevertheless, in some applications, it is enough to fine-tune the accelerators' behavior instead of changing them entirely. In these cases, rather than allocating new accelerators, it is possible to reconfigure individual logic elements of the circuit, such as look-up tables or flip-flops. There is also an intermediate approach that targets the reconfigurability of accelerators composed of several tightly interconnected modules, such as overlays. In those architectures, it is possible to reconfigure only the modules that differ between the existing accelerator versions, thus reducing the reconfigurable footprint granularity. This paper proposes a classification of the approaches above, categorizing them as coarse, fine, and medium grain, respectively. There are neither commercial nor academic tools supporting multi-grain reconfiguration to take advantage of each granularity strength on commercial FPGAs. Differently, this paper proposes a tool called IMPRESS, that provides design-time and run-time support for multi-grain reconfiguration in Xilinx 7 Series FPGAs. Specific criteria are provided to combine the different granularity levels, trading off the benefits in terms of flexibility and performance, with different design and run-time costs. Two use cases in the image processing and neural network domains have been implemented to show how IMPRESS can build multi-grain reconfigurable systems.

show abstract

“…Um delesé aumentar o desempenho e eficiência da comunicacão entre a nuvem e os chamados end devices, visando a implementação de sistemas sensíveisà latência (Mouradian et al, 2018). Diversas aplicações que requerem análise em tempo real de dados provenientes de sensores complexos, comoé o caso das câmeras, são incluídas nessa categoria, sendo exemplos o monitoramento de qualidade de produtos por meio de visão computacional, aplicações para detecção e combate a incêndios e veículos conectados, além das redes inteligentes (Nguyen and C. Hoe, 2018).…”

Section: Introductionunclassified

Uma Metodologia de Projeto para Reconfiguração Parcial e Dinâmica em Aplicações de Fog-Computing

Castro

Arias-García

Dias

2019

Anais Do 14º Simpósio Brasileiro De Automação Inteligente

View full text Add to dashboard Cite

Cloud computing has been increasingly used in industrial environments. This decentralized computing architecture promotes cost reduction, reduces the time-to-market and improves flexibility. However, a common side-effect of this approach is an increase in latency. Fog-computing is an ideal solution to this latency-sensitive applications as it allows the edgedevices to carry out a substantial amount of computation locally. Reconfigurable architectures implemented in SoC-FPGAs meet those requirements, especially when Dynamic and Partial Reconfiguration (DPR) is used. Using DPR is challenging, however, as architectural design can be complex without supporting methodologies and architectural models. This work presents a methodology and a supporting architectural model for the application of Dynamic and Partial Reconfiguration in SoC-FPGAs targeting fog-computing applications to the industry 4.0. The methodology and architecture proposed have been applied with success to an illustrative example. Resumo: Recentemente, observa-se um crescimento da utilização de computação em nuvem na indústria. Esse modelo permite a descentralização da infraestrutura, reduzindo custos, diminuindo o time-to-market (TTM) e aumentando a flexibilidade. No entanto, um efeito colateral dessa abordagemé o aumento da latência. Para sistemas sensíveisà latência, fogcomputing se apresenta como uma solução ideal, pois parte da computaçãoé realizada nos dispositivos de fronteira. Arquiteturas reconfiguráveis implementadas em SoC-FPGAs mostramse eficientes para atender tais requisitos, especialmente quando empregada reconfiguração parcial e dinâmica. Uma dificuldade dessa abordagemé a complexidade do projeto que requer um suporte de metodologias e modelos de arquitetura adequados. Nesse trabalho apresenta-se uma proposta de arquitetura e de metodologia para aplicar a técnica de reconfiguração parcial e dinâmica em plataformas SoC-FPGAs em aplicações de fog-computing para indústria 4.0. A metodologia e arquitetura proposta são aplicadas com sucesso em um exemplo ilustrativo.

show abstract

Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration

Cited by 8 publications

References 7 publications

Partial Reconfiguration for Design Optimization

Partial Reconfiguration for Design Optimization

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

Uma Metodologia de Projeto para Reconfiguração Parcial e Dinâmica em Aplicações de Fog-Computing

Contact Info

Product

Resources

About