A comparison of dynamic branch predictors that use two levels of branch history

Yeh, Tse-Yu; Patt, Yale N.

doi:10.1145/165123.165161

Cited by 233 publications

(98 citation statements)

References 7 publications

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“…The history information can be maintained in a single global branch history register (BHR), in separate per-address registers where each address is a branch instruction, or in separate per-set registers. Moreover, the global pattern history table (PHT) may be a single table that contains the secondlevel history information, or multiple tables where each branch instruction identified by its address has its own second-level pattern table [9]. The PHT contains l-bit counters which represent the value according to which the branch is predicted.…”

Section: Related Workmentioning

confidence: 99%

Generalized Worst Case Estimation of Misprediction Counts for Dynamic Branch Predictors

Elmenyawi¹

2017

IJCDS

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Estimating the number of mispredictions is critically important for estimating the Worst-Case Execution Time for real-time systems. This paper generalizes and improves over previous attempts to provide a safe and tight mispredication count estimate for dynamic branch predictors. The paper gives closed formulas to compute mispredictions in case of simple and nested loops applicable to all variations of two-level adaptive branch predictors in addition to the gshare and gselect predictors. The given formulas are general enough to accommodate predictors with any counter size.

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Section: Related Workmentioning

confidence: 99%

Generalized Worst Case Estimation of Misprediction Counts for Dynamic Branch Predictors

Elmenyawi¹

2017

IJCDS

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“…The fetch unit has a great role in prediction mechanism [2] in parallel register sharing architecture but Pan, So and Rahmeh (1992) [14], and Yeh Y. Patt (1993) [16] proposed some recent prediction mechanism that do not require the addresses of branches for prediction rather there is requirement of identity of each branch to be known so that the predicted target address can be obtained using either BTB [7] or by decoding branch instructions in parallel register sharing architecture. There are so many commercially available embedded processors that are capable to extend the set of base instructions for a specific application domain.…”

Section: Related Workmentioning

confidence: 99%

Role of Multiblocks in Control Flow Prediction using Parallel Register Sharing Architecture

Kumar¹,

Singh²

2010

IJCA

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In this paper we present control flow prediction (CFP) in parallel register sharing architecture to achieve high degree of ILP. The main idea behind this concept is to use a step beyond the prediction of common branch and permitting the architecture to have the information about the CFG (Control Flow Graph) components of the program to have better branch decision for ILP. The navigation bandwidth of prediction mechanism depends upon the degree of ILP. It can be increased by increasing control flow prediction at compile time. By this the size of initiation is increased that allows the overlapped execution of multiple independent flow of control. The multiple branch instruction can also be allowed. These are intermediate steps to be taken in order to increase the size of dynamic window to achieve a high degree of instruction level parallelism exploitation.

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“…There is a 64-entry 4-way set associative instruction TLB and 128-entry 4-way set associative data TLB, each with a 30-cycle miss penalty. For this study, we used the GAp branch predictor [24,25]. The predictor has a 4K-entry Pattern History Table (PHT) with 2-bit saturating counters.…”

Section: Microarchitecturementioning

confidence: 99%

Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions

Sendag

Lilja

Kunkel³

2002

Euro-Par 2002 Parallel Processing

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Abstract.As the degree of instruction-level parallelism in superscalar architectures increases, the gap between processor and memory performance continues to grow requiring more aggressive techniques to increase the performance of the memory system. We propose a new technique, which is based on the wrong-path execution of loads far beyond instruction fetch-limiting conditional branches, to exploit more instruction-level parallelism by reducing the impact of memory delays. We examine the effects of the execution of loads down the wrong branch path on the performance of an aggressive issue processor. We find that, by continuing to execute the loads issued in the mispredicted path, even after the branch is resolved, we can actually reduce the cache misses observed on the correctly executed path. This wrong-path execution of loads can result in a speedup of up to 5% due to an indirect prefetching effect that brings data or instruction blocks into the cache for instructions subsequently issued on the correctly predicted path. However, it also can increase the amount of memory traffic and can pollute the cache. We propose the Wrong Path Cache (WPC) to eliminate the cache pollution caused by the execution of loads down mispredicted branch paths. For the configurations tested, fetching the results of wrong path loads into a fully associative 8-entry WPC can result in a 12% to 39% reduction in L1 data cache misses and in a speedup of up to 37%, with an average speedup of 9%, over the baseline processor.

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A comparison of dynamic branch predictors that use two levels of branch history

Cited by 233 publications

References 7 publications

Generalized Worst Case Estimation of Misprediction Counts for Dynamic Branch Predictors

Generalized Worst Case Estimation of Misprediction Counts for Dynamic Branch Predictors

Role of Multiblocks in Control Flow Prediction using Parallel Register Sharing Architecture

Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions

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