A Comparison Among DPI Immunities of Multi-Stage CSVCOs and Ring Oscillators

Khan, Qazi Mashaal; Ramezani, Akram; Koohestani, Mohsen; Ramdani, Mohamed; Perdriau, Richard

doi:10.1109/emccompo52133.2022.9758599

Cited by 5 publications

(9 citation statements)

References 13 publications

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“…1). They were integrated, among other structures, into the 1.52 mm × 1.52 mm PETER ESEO research die [23], which was fabricated in silicon-on-insulator (SOI) CMOS 180 nm 5 V technology. They were designed to have matching aspect ratios and generate sinusoidal signals with stable output frequencies.…”

Section: A Ic and Pcb Design Descriptionmentioning

confidence: 99%

Influence of Temperature on the EFT Immunity of Multistage Integrated Oscillators

Khan

Koohestani

Perdriau

2023

IEEE Trans. Electromagn. Compat.

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The reliable operation of an integrated circuit (IC) can be affected by transient electromagnetic disturbances and temperature variations. In this paper, the performance of three oscillator circuits, namely 3-and 5-stage current-starved voltage controlled oscillators and a 3-stage ring oscillator, is compared with respect to electrical fast transients (EFT) under the influence of thermal stress. The main objective is to compare and assess, by means of measurements, the EFT immunities of integrated oscillators with the same electrostatic discharge (ESD) protections but different circuit topologies. The failure modes caused by EFT are proposed based on the considered failure criterion, i.e. the output frequency of the oscillator. Moreover, the importance of the IC package on the immunity levels of each oscillator is investigated. Additionally, the output frequency response of each oscillator to the combined EFT and temperature stresses is analyzed without the external parasitic effects. The results show that the 5-stage CSVCO is the most resilient oscillator to temperature variations, whereas it is the least immune to the combined effect of EFT and temperature. Moreover, a distinct behavior in each tested oscillator's frequency is observed for the in-phase EFT injections due to the topology of the circuit. Relevant MOSFET characteristics such as on-state drain-tosource resistance, drain currents, power dissipation, effective mobility and threshold voltage level are further analyzed under the influence of thermal stress and EFT disturbances. The root cause of higher EFT susceptibility of the 5-stage CSVCO is found to be the considerable variation of the on-state resistance due to the combined reduction of effective mobility and absolute threshold voltage levels of the MOSFETs. As a result, the power dissipation rises and causes thermal runaway.

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Section: A Ic and Pcb Design Descriptionmentioning

confidence: 99%

Influence of Temperature on the EFT Immunity of Multistage Integrated Oscillators

Khan

Koohestani

Perdriau

2023

IEEE Trans. Electromagn. Compat.

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“…For this analysis, two conventional three-stage oscillators, a CSVCO and RO were selected. They are integrated, among other circuits, into the 1.52 mm × 1.52 mm PETER_ESEO research die [29], which is fabricated in silicon-on-insulator (SOI) CMOS 180 nm 5 V technology through the XFAB foundry. They were designed to have matching aspect ratios and fixed output frequency values.…”

Section: A Ic Design Descriptionmentioning

confidence: 99%

“…The output of each oscillator was monitored, for the input EM disturbances having the same random phase, at ambient and at extreme temperatures. The oscillators under study were susceptible to single-tone EM disturbances from 100 MHz to 1 GHz [29]. Within this range a total of 10 single-tone EMI frequencies were selected with a step size of 100 MHz.…”

Section: A Multitone Test Setup Descriptionmentioning

confidence: 99%

Experimental Characterization of Multitone EM Immunity of Integrated Oscillators Under Thermal Stress

et al. 2022

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The reliable operation of an integrated circuit can be affected by environmental changes, such as of multiple frequency electromagnetic (EM) disturbances and temperature variations. This paper compares the performance of two oscillator circuits, namely a current-starved voltage controlled oscillator and a ring oscillator integrated into a chip, in terms of their immunity to multitone direct power injection while under the influence of thermal stress. The objective is to demonstrate by the means of measurements the synergistic effect caused by multitone EM disturbances in a test chip, in contrast to the conventional single-tone EM disturbances. Moreover, the multitone immunity levels of integrated blocks with different architectures but similar functionality are analyzed at extreme temperature deviations. Bayesian networks (BN) are applied in order to visualize the probability of circuit failure due to multitone disturbances and temperature influence. Additionally, noisy-OR and improved-adaptive-recursive-noisy-OR (I-ARNOR) probabilistic models are implemented to identify the types of causal interactions (i.e. inhibition and positive causality) between multitone disturbances and to predict the probability of failure due to higher order multitone disturbances, respectively.

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“…A VCO is generally used to drive internal blocks such as phase locked loops. The PETER ESEO IC is designed to be manufactured in silicon-on-insulator CMOS 5 V using 180 nm technology kit, provided by the XFAB foundry [20]. The function of the CSVCO is to provide an output voltage at a nominal frequency of F 1 = 703 MHz, for a given control input V C = 1.8 V and isolated supply voltage…”

Section: A Model Descriptionmentioning

confidence: 99%

“…The frequencies for the multitone simulations were selected from the range 50-950 MHz as this CSVCO design was found to be susceptible in this band in an earlier study [20] and is within the frequency scope of [1].…”

Section: A Model Descriptionmentioning

confidence: 99%

Application of Probabilistic Models for Multitone Electromagnetic Immunity Analysis

Devaraj

Khan

Ruddle

et al. 2022

IEEE Trans. Electromagn. Compat.

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The operational environment of modern electronic systems may include multiple frequency electromagnetic disturbances. However, immunity measurements usually employ single frequency continuous waveforms (i.e. single-tones). The performance of two oscillator circuits with different topologies (one simulated and one measured) were used as case studies to investigate immunity to simultaneous single-tone disturbances (i.e. multitones) using probabilistic Bayesian network models. For the multitone analysis, the noisy-OR model was first used to identify the type of causal interactions between simultaneously occurring single-tones. Probabilistic theories derived from the recursive noisy-OR model, which inherits the independence assumptions of the noisy-OR and any known causal dependence between simultaneously occurring single-tones, were then used to predict the probability of higher order multitone failures. For the two case studies, the probability of three-tone failures was estimated using the single-tone and two-tone failure probability values. An improved adaptive recursive noisy-OR model was also proposed to overcome the practical difficulties of obtaining multitone failure probabilities, from either simulations or measurements.

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A Comparison Among DPI Immunities of Multi-Stage CSVCOs and Ring Oscillators

Cited by 5 publications

References 13 publications

Influence of Temperature on the EFT Immunity of Multistage Integrated Oscillators

Influence of Temperature on the EFT Immunity of Multistage Integrated Oscillators

Experimental Characterization of Multitone EM Immunity of Integrated Oscillators Under Thermal Stress

Application of Probabilistic Models for Multitone Electromagnetic Immunity Analysis

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