Influence of Temperature on the EFT Immunity of Multistage Integrated Oscillators

Abstract

The reliable operation of an integrated circuit (IC) can be affected by transient electromagnetic disturbances and temperature variations. In this paper, the performance of three oscillator circuits, namely 3-and 5-stage current-starved voltage controlled oscillators and a 3-stage ring oscillator, is compared with respect to electrical fast transients (EFT) under the influence of thermal stress. The main objective is to compare and assess, by means of measurements, the EFT immunities of integrated oscillators with the same electrostatic discharge (ESD) protections but different circuit topologies. The failure modes caused by EFT are proposed based on the considered failure criterion, i.e. the output frequency of the oscillator. Moreover, the importance of the IC package on the immunity levels of each oscillator is investigated. Additionally, the output frequency response of each oscillator to the combined EFT and temperature stresses is analyzed without the external parasitic effects. The results show that the 5-stage CSVCO is the most resilient oscillator to temperature variations, whereas it is the least immune to the combined effect of EFT and temperature. Moreover, a distinct behavior in each tested oscillator's frequency is observed for the in-phase EFT injections due to the topology of the circuit. Relevant MOSFET characteristics such as on-state drain-tosource resistance, drain currents, power dissipation, effective mobility and threshold voltage level are further analyzed under the influence of thermal stress and EFT disturbances. The root cause of higher EFT susceptibility of the 5-stage CSVCO is found to be the considerable variation of the on-state resistance due to the combined reduction of effective mobility and absolute threshold voltage levels of the MOSFETs. As a result, the power dissipation rises and causes thermal runaway.

Validation of IC Conducted Emission and Immunity Models Including Aging and Thermal Stress

“…In comparison with aging, thermal stress can temporarily raise junction temperatures of CMOS transistors in the tested circuit and create a drift in their V th , µ eff , and drain current levels [50]. Although no permanent degradation mechanisms occur, these drifts can cause unexpected conducted emission levels.…”

“…This is due to thermal stress causing a drift in µ eff and V th levels of the latter. Further explanation of the influence of temperature on physical transistor parameters, i.e., V th and µ eff , as well as their relation to the EMC behavior of the integrated blocks can be found in [50].…”