A Comparative Study on the Soft-Error Rate of Flip-Flops from 90-nm Production Libraries

Heijmen, T.; Roché, Philippe; Gasiot, Gilles; Forbes, K.R.

doi:10.1109/relphy.2006.251218

Cited by 24 publications

(8 citation statements)

References 26 publications

(42 reference statements)

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“…Effects of variability on error rate in the literature has mostly been addressed through critical charge modeling in different process corners or analytical modeling [4][5][6][7][8][9][10] or through critical charge spread modeling with monte-carlo drawing of transistor parameters [11][12][13][14]. Few alpha experimental results are available in the literature and no neutron data has ever been reported.…”

Section: Introductionmentioning

confidence: 99%

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

Gasiot

Glorieux

Uznanski

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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This paper shows alpha and neutron experimental Soft Error Rate characterization of a SRAM test vehicle processed with different process corners in order to emulate the variability encountered in volume production. It allows assessing large variability effects with few samples that are compatible with accelerated SER testing. This allows investigating the effect of variability in mass-production on soft error rate of decananometric technologies. Keywords-Process corner; Soft Error Rate; alpha and neutron experiments;manufacturing process variability; volume productionI.

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Section: Introductionmentioning

confidence: 99%

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

Gasiot

Glorieux

Uznanski

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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“…A sufficient amount of accumulated charge may invert the state of a logic device thereby introducing a logical fault into the circuit's operation. At sea level, alpha particle is the major cause of the total transient failures [8]. Fortunately, not all of the transient faults will show up as architecture errors.…”

Section: B Soft Error In Cache Memorymentioning

confidence: 99%

Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache

Sun

Liu

et al. 2012

IEEE Trans. VLSI Syst.

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Due to its great scalability, fast read access, low leakage power, and nonvolatility, magnetic random access memory (MRAM) appears to be a promising memory technology for on-chip cache memory in microprocessors. However, the write-to-MRAM process is relatively slow and results in high dynamic power consumption. Such inherent disadvantages of MRAM make researchers easily conclude that MRAM can only be used for low-level caches (e.g., L2 or L3 cache), where cache memories are less frequently accessed and slow write to MRAM can be more easily compensated using simple architectural techniques. By developing a hybrid cache architecture, this paper attempts to show that, with appropriate architecture design, MRAM can also be used in L1 cache to improve both the energy efficiency and soft error immunity. The basic idea is to supplement the MRAM L1 cache with several small SRAM buffers, which can substantially mitigate the performance degradation and dynamic energy overhead induced by MRAM write operations. Moreover, the proposed hybrid cache architecture is also an efficient solution to protect cache memory from radiation-induced soft errors, as MRAM is inherently invulnerable to emissive particles. Simulation results show that, with only less than 2% performance degradation, the proposed design approach can reduce the power consumption by up to 76.1% on average compared with the traditional SRAM L1 cache. In addition, the architectural vulnerability factor of L1 data cache is reduced from 28.3% to as low as 0.5%.Index Terms-Cache, low power, magnetic RAM (MRAM), reliability, soft error.

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“…With continued scaling, however, Qcrit for latches and flip-flops continues to decrease. Soft Errors in latches and dynamic circuits is an active topic of research [3].…”

Section: Introductionmentioning

confidence: 99%

Protecting Big Blue from Rogue Subatomic Particles

Cannon¹,

KleinOsowski

Gordon³

et al. 2007

2007 IEEE International Conference on Integrated Circuit Design and Technology

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Fig. 1. Representative SOI transistor showing the column of charge generated from an a-particle strike. Figure reproduced from [1].Abstract-Device technology scaling continues to deliver faster and smaller transistors, contributing to IBMs continued leadership in Server Systems. However, there is also a dark side to device technology scaling... As transistors shrink, the amount of charge required to change the logic state of a memory or a logic circuit (i.e. flip a 1 to a 0 and vice versa) also shrinks. This complication spurs continued effort at IBM to test, characterize, and mitigate these transient bit flips, so called soft errors. In this paper we survey our ongoing work in this realm and introduce our views on trends for soft errors in future device technologies.

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A Comparative Study on the Soft-Error Rate of Flip-Flops from 90-nm Production Libraries

Cited by 24 publications

References 26 publications

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache

Protecting Big Blue from Rogue Subatomic Particles

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