A comparative study on the accuracy of small-signal equivalent circuit modeling for large gate periphery GaN HEMT with different source to drain length and gate width

Anand, Ashima; Reeta, None; Rawal, D. S.; Narang, Rakhi; Mishra, Meenal; Saxena, Manoj; Gupta, Mridula

doi:10.1016/j.mejo.2021.105258

Cited by 9 publications

(8 citation statements)

References 21 publications

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“…The conventional approach has been considered for extraction of parameters and has been depicted as a flow chart in figure 3. First, the experimental [19] S-parameter at Vgs=-5 V and Vds=0 V (cold pinch off condition) is used to estimate the pad capacitances. When determining the parasitic inductances and resistances, Vgs and Vds in a cold HEMT measurement, i.e., 0 V. The curve fitting method is then applied to quantify the resistances and inductances.…”

Section: Extraction Methodologymentioning

confidence: 99%

GaN HEMT Device Model Development for Implementation of Different Circuit

Gupta

2023

ISPS'23 Proceedings

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GaN HEMT devices (with different dimensions) have been investigated using 16- and 22-element smallsignal equivalent circuit Model. The percentage error is estimated to show the difference in extracted parameters using 16- and 22-element small-signal equivalent circuit model which assist in choosing the accurate small-signal model for large gate periphery GaN HEMTs. For device’s low power operation linear models are sufficient. In order to achieve higher certainty for high power applications, the nonlinear behaviour of the device must be considered. While generating the large-signal device model, the nonlinear capacitances Cgs and Cgd, as well as the current source Ids are primarily considered to capture the non-linear behavior of the device. The capacitances, Cgs and Cgd, are dependent on applied bias i. e. V gs and Vds. The Angelov model for Ids is used to generate the non-linear model parameters which uses the multi-bias small-signal equivalent circuit parameters.

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Section: Extraction Methodologymentioning

confidence: 99%

GaN HEMT Device Model Development for Implementation of Different Circuit

Gupta

2023

ISPS'23 Proceedings

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“…The pulsed S-parameters were recorded for different pulse widths similar to section 3.4 while keeping the pulse period fixed at 1 ms. A 22-element smallsignal parameter extraction strategy was adopted based on the methodology put forward by Jarndal and Kompa [54]. As demonstrated and validated experimentally by Anand et al [55], TCAD simulation in general cannot capture the pad and inter-electrode parasitics, nonetheless it can be used to investigate the changes in an intrinsic FET for different device architectures. The 22-element small-signal circuit proposed by Jarndal et al [54] dictates transistor operation for different biasing conditions.…”

Section: Insight Into An Intrinsic Transistor Using DC and Pulsed Sca...mentioning

confidence: 99%

“…These were extracted by recording the S-parameters with V GS = 0 V and V DS = 0 V, often regarded as the cold bias condition. Employing the extraction methodology [54], these S-parameters yield parasitic inductances (L G , L S , L D ) and parasitic series resistances (R G , R S , R D ) associated with the Ohmic and Schottky contacts [54,55]. Similarly, by recording the S-parameters in a cold pinch-off condition, i.e.…”

Section: Insight Into An Intrinsic Transistor Using DC and Pulsed Sca...mentioning

confidence: 99%

“…Similarly, by recording the S-parameters in a cold pinch-off condition, i.e. at V GS = −5 V and V DS = 0 V, interelectrode (C pgi , C pdi , C gdi ) and pad (C pga , C pda , C gda ) capacitances can be extracted [54,55].…”

Section: Insight Into An Intrinsic Transistor Using DC and Pulsed Sca...mentioning

confidence: 99%

“…Following the extraction of extrinsic elements, intrinsic elements were extracted by adopting the de-embedding procedure [54,55] for different biasing conditions in both DC and pulsed mode operation. The intrinsic elements extracted at V GS = −1 V and V DS = 10 V using static I-V conditions are compiled in table 6.…”

Section: Insight Into An Intrinsic Transistor Using DC and Pulsed Sca...mentioning

confidence: 99%

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Efficacy of back barrier engineered Π-gate InAlN/GaN high electron mobility transistors for high-power applications

Sehra

Anand

Saraswat

et al. 2023

J. Phys. D: Appl. Phys.

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This work investigates the thin barrier InAlN/GaN HEMTs for high power applications through TCAD simulations. To begin with, the TCAD simulations were first calibrated with the in – house fabricated InAlN HEMT sample for both DC and Pulsed characteristics. The thin barrier InAlN/GaN HEMTs shows a large leakage current through the gate electrode due to a high gate injection which severely degrades the breakdown characteristics of the device and thus acts as a bottleneck for high power applications. To improve the 2DEG confinement and to consequently reduce the bulk leakage, back – barrier technique is used. The resistive GaN buffer is replaced with AlGaN back – barrier which improves the breakdown characteristics at the cost of output power density. Thus, to scale up the output power density, and further optimize the breakdown characteristics, a Π – shaped Gate is introduced to limit the gate leakage current through the InAlN barrier by virtue of its improved hot electron reliability. Coupled with the AlGaN back – barrier, the Π – Gate significantly improves the breakdown characteristics for achieving high output power densities, albeit with minor trade – offs to the device gain. To elucidate the compatibility towards high power applications, all the device architectures are dynamically characterized by Pulsed IV simulations and the trap related dispersive effects are investigated. Amongst all, the Π – shaped Gate coupled with the AlGaN back – barrier outperforms the conventional architectures by exercising superior electrostatic control over the channel and exhibiting a high linearity for high power mm – Wave applications.

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