A comparative study of lifetime reliability of planar MOSFET and FinFET due to BTI for the 16 nm CMOS technology node based on reaction-diffusion model

Mahmoud, Mohamed Mounir; Soin, Norhayati

doi:10.1016/j.microrel.2019.03.007

Cited by 15 publications

(6 citation statements)

References 31 publications

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“…High voltage operations of transistors introduce many reliability issues such as Time-Dependent Dielectric Breakdown (TDDB), Bias Temperature Instability (BTI), and Hot-Carrier Injection (HCI). These are the dominant causes of aging in scaled technology nodes (45nm and below) [61]. In older nodes, Electromigration (EM) also plays a key role [23, 25-30, 69, 79].…”

Section: Transistor Aging In Neuromorphic Hardwarementioning

confidence: 99%

Dynamic Reliability Management in Neuromorphic Computing

Song

Hanamshet

Balaji

et al. 2021

J. Emerg. Technol. Comput. Syst.

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Neuromorphic computing systems execute machine learning tasks designed with spiking neural networks. These systems are embracing non-volatile memory to implement high-density and low-energy synaptic storage. Elevated voltages and currents needed to operate non-volatile memories cause aging of CMOS-based transistors in each neuron and synapse circuit in the hardware, drifting the transistor’s parameters from their nominal values. If these circuits are used continuously for too long, the parameter drifts cannot be reversed, resulting in permanent degradation of circuit performance over time, eventually leading to hardware faults. Aggressive device scaling increases power density and temperature, which further accelerates the aging, challenging the reliable operation of neuromorphic systems. Existing reliability-oriented techniques periodically de-stress all neuron and synapse circuits in the hardware at fixed intervals, assuming worst-case operating conditions, without actually tracking their aging at run-time. To de-stress these circuits, normal operation must be interrupted, which introduces latency in spike generation and propagation, impacting the inter-spike interval and hence, performance (e.g., accuracy). We observe that in contrast to long-term aging, which permanently damages the hardware, short-term aging in scaled CMOS transistors is mostly due to bias temperature instability. The latter is heavily workload-dependent and, more importantly, partially reversible. We propose a new architectural technique to mitigate the aging-related reliability problems in neuromorphic systems by designing an intelligent run-time manager (NCRTM), which dynamically de-stresses neuron and synapse circuits in response to the short-term aging in their CMOS transistors during the execution of machine learning workloads, with the objective of meeting a reliability target. NCRTM de-stresses these circuits only when it is absolutely necessary to do so, otherwise reducing the performance impact by scheduling de-stress operations off the critical path. We evaluate NCRTM with state-of-the-art machine learning workloads on a neuromorphic hardware. Our results demonstrate that NCRTM significantly improves the reliability of neuromorphic hardware, with marginal impact on performance.

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Section: Transistor Aging In Neuromorphic Hardwarementioning

confidence: 99%

Dynamic Reliability Management in Neuromorphic Computing

Song

Hanamshet

Balaji

et al. 2021

J. Emerg. Technol. Comput. Syst.

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“…In [ 10 ], the author reveals that the NBTI recovery mechanism is more important in a 20 nm MOSFET than in a 14 nm FinFET, which may explain why the overall degradation due to NBTI is greater in the FinFET [ 9 ]. A simulation based on the diffusion–reaction model of a 16 nm MOSFET and FinFET is performed in [ 11 ] and indicates that the propagation delay degradation is

higher in MOSFET. In [ 9 ], the author shows that the HCI is lower in the FinFET than in the MOSFET for low drain voltages, and this trend reverses for high drain voltages.…”

Section: Introductionmentioning

confidence: 99%

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

Sobas,

Marc

2023

Micromachines

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Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions (Vnom≤Vstress≤1.3Vnom and 25°C≤Tstress≤115°C) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between 50% and 70% of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of 1%, which is a first indicator proving the FPGAs’ good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA.

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“…At the 5-nm technology node, comparisons have been made of transistor performance between FinFET and gate-all-around (GAA) technologies with actual gate lengths of 16 nm [ 5 ]. In regard to 16-nm CMOS technology, comparative studies of lifetime reliability between planar MOSFETs with a gate length of 30 nm and FinFETs with a gate length of 20 nm have been undertaken [ 6 ].…”

Section: Introductionmentioning

confidence: 99%

“…However, FinFETs are susceptible to self-heating and are more expensive than traditional planar transistors. Comparative studies investigating the effects of bias temperature instability on lifetime reliability indicate trade-offs between planar MOSFETs and FinFETs in advanced nodes such as 16 nm [ 6 ]. Therefore, planar bulk MOSFET technology using mature and conventional processing technologies can be an alternative manufacturing option compared to the FDSOI and FinFET approaches beyond 28 nm, if unwanted SCEs can be suppressed [ 27 ].…”

Section: Introductionmentioning

confidence: 99%

“…However, FinFETs are susceptible to self-heating and are more expensive than traditional planar transistors. Comparative studies investigating the effects of bias temperature instability on lifetime reliability indicate trade-offs between planar MOSFETs and FinFETs in advanced nodes such as 16 nm [6]. Therefore, planar bulk MOSFET technology using Many mid-tier mobile phone applications do not need the highest performance, but they are also susceptible to power efficiency issues.…”

Section: Introductionmentioning

confidence: 99%

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A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length

et al. 2021

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At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.

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A comparative study of lifetime reliability of planar MOSFET and FinFET due to BTI for the 16 nm CMOS technology node based on reaction-diffusion model

Cited by 15 publications

References 31 publications

Dynamic Reliability Management in Neuromorphic Computing

Dynamic Reliability Management in Neuromorphic Computing

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length

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A comparative study of lifetime reliability of planar MOSFET and FinFET due to BTI for the 16 nm CMOS technology node based on reaction-diffusion model

Cited by 15 publications

References 31 publications

Dynamic Reliability Management in Neuromorphic Computing

Dynamic Reliability Management in Neuromorphic Computing

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length

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A comparative study of lifetime reliability of planar MOSFET and FinFET due to BTI for the 16 nm CMOS technology node based on reaction-diffusion model