A compaction method for full chip VLSI layouts

Dao, Joseph; Matsumoto, Nobu; Hamai, T.; Ogawa, Chusei; Mori, Shoji

doi:10.1145/157485.164953

Cited by 9 publications

(2 citation statements)

References 7 publications

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“…The three most dominant layout automation techniques have been schematic driven layout synthesis [4], symbolic layout with compaction [5] [6], and procedural module generation [7] [8].…”

Section: Figure 1 Library Development Flow With Manual Layoutmentioning

confidence: 99%

Developing a concurrent methodology for standard-cell library generation

Baltus

Varga

Armstrong

et al. 1997

Proceedings of the 34th Annual Conference on Design Automation Conference - DAC '97

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-This paper describes the development of a concurrent methodology for standard cell library generation. Use of a novel physical design automation method enables a high degree of concurrency among process, circuit, and layout development. In addition to reducing overall time-to-market, the new method allows optimization to occur simultaneously across the circuit, layout, and process design spaces. The result is libraries with improved density, circuit performance, and process yield.

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“…The three most dominant layout automation techniques have been schematic driven layout synthesis [4], symbolic layout with compaction [5] [6], and procedural module generation [7] [8].…”

Section: Figure 1 Library Development Flow With Manual Layoutmentioning

confidence: 99%

Developing a concurrent methodology for standard-cell library generation

Baltus

Varga

Armstrong

et al. 1997

Proceedings of the 34th Annual Conference on Design Automation Conference - DAC '97

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show abstract

“…Currently available layout migration algorithms were classified into constraint graph based [1,2,3] and integer linear programming based [4,5,6,7] algorithms. Constraint graph based algorithms usually scans all components via a virtual scan line of the design and then constructs a constraint graph.…”

Section: Introductionmentioning

confidence: 99%

Topology-driven cell layout migration with collinear constraints

Chaung

Lin

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-Traditional layout migration focuses on area minimization, thus suffered wire distortion, which caused loss of layout topology. A migrated layout inheriting original topology owns original design intention and predictable property, such as wire length which determines the path delay importantly. This work presents a new rectangular topological layout to preserve layout topology and combine its flexibility of handling wires with traditional scan-line based compaction algorithm for area minimization. The proposed migration flow contains devices and wires extraction, topological layout construction, unidirectional compression combining scan-line algorithm with collinear equation solver, and wire restoration. Experimental results show that cell topology is well preserved, and a several times runtime speedup is achieved as compared with recent migration research based on ILP (integer linear programming) formulation. I. INTRODUCTIONManufacturing technology has been working on decreasing feature size. Handcrafted re-design of a chip layout and cell library conforming to new manufacturing technology design rules spends considerable time. Moreover, a cost-down issue emerges from the product in severe competitions. Seeking a semiconductor foundry with decreased manufacture cost is an alternative solution. Two semiconductor foundries generally vary in the two manufacture technologies design rules of the same generation, and it demands numerous layout modifications to satisfy the target design rules.Traditional goal of layout migration is to efficiently shrink and place each component in the layout as compact as possible. Currently available layout migration algorithms were classified into constraint graph based [1,2,3] and integer linear programming based [4,5,6,7] algorithms. Constraint graph based algorithms usually scans all components via a virtual scan line of the design and then constructs a constraint graph. New design rules are then employed on the graph to identify the position of every component with the longest path algorithm. However, the conventional constraint graph algorithm intends to produce a compact layout with numerous changes in interconnection shapes and topologies because it only considers space utilization. The resultant changes in the shape and topology degrade the timing delay and other properties. With original design intention destroyed, designers must spend time comprehending and modifying the migration layout. The bulky burden lowers the availability of layout migration. Heng et al. proposed a minimum perturbation (MP) objective function to preserve original design intention by minimizing the position changes of all edges [6]. To improve the MP objective function, Fang et al. considered that the effect of geometric changed by accumulating the effect of position changing in subsequently processed objects [7]. The integer linear programming approach can not guarantee that the relative relations among an object, and its neighbors are kept unchanged. For example, an object A initially pla...

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Extending pitchmatching algorithms to layouts with multiple grid constraints

Miyashita¹

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 With EDA Technofair

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A compaction method for full chip VLSI layouts

Cited by 9 publications

References 7 publications

Developing a concurrent methodology for standard-cell library generation

Developing a concurrent methodology for standard-cell library generation

Topology-driven cell layout migration with collinear constraints

Extending pitchmatching algorithms to layouts with multiple grid constraints

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