A Compact Test Structure for Characterizing Transistor Variability Beyond &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$3\sigma $ &lt;/tex-math&gt;&lt;/inline-formula&gt;

Chen, Christopher; Li, Liping; Lim, Queennie; HaiTeh, Hong; Teh, Hong Hai; Omar, Noor Fadillah Binti; Ler, Chun-Lee; Ler, Chun Lee; Watt, J.T.

doi:10.1109/tsm.2015.2439275

Cited by 15 publications

(2 citation statements)

References 28 publications

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“…With the device dimensions scale down to the nanoscale regime, the device variability has taken a crucial relevance into the device's behavior [3]. In this context, RRAM intrinsic variability challenge has driven special attention to test structures [4][5]. The role of test structures in the development and monitoring of a technology and its applications has become ever more important as alternative hybrid technologies (i.e., CMOS combined with RRAM technologies) are introduced to go beyond Von Neumann architectures [6].…”

Section: Introductionmentioning

confidence: 99%

STATE: A Test Structure for Rapid Prediction of Resistive RAM Electrical Parameter Variability

Aziza

Postel-Pellerin

Bazzi

et al. 2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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Resistive RAM (RRAM) design optimization and reliability monitoring is essential not only to gain market share in the highly competitive emerging memory sector, but also to enable future high-capacity and power-efficient braininspired systems, beyond the capabilities of today's hardware. Common problems with RRAM are related to high variability in operating conditions and low yield. Although research has taken steps to resolve these issues, variability remains a major hurdle for the wide spread of the technology. In this paper, a novel test structure consisting of an array of non-addressable 1T-1R RRAM memory cells with parallel connection of all memory elements is introduced. The test structure can be used as a powerful tool for process variation monitoring during a new process technology introduction and also for marginal cell populations detection during process maturity. The test structure is designed to measure RRAM parameters of interest based on a simple measurement methodology: from the transfer characteristic measured under the select transistor clamping bias, it is possible to obtain accurate information on the RRAM switching parameters as well as the ON/OFF resistance values.

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Section: Introductionmentioning

confidence: 99%

STATE: A Test Structure for Rapid Prediction of Resistive RAM Electrical Parameter Variability

Aziza

Postel-Pellerin

Bazzi

et al. 2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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show abstract

“…[1][2][3] There are numerous reports of measurement circuits for characterizing leakage current and threshold voltage variations. [4][5][6][7][8][9][10] However, most of the measurements are performed in a device matrix where the devices are placed in a highly regular layout. The devices are often placed with low density compared to that found in a design performed with an automatic place and route design.…”

Section: Introductionmentioning

confidence: 99%

On-chip leakage current variation measurement using external-reference-free current-to-time conversion for densely placed MOSFETs

Islam

Harada

2022

Jpn. J. Appl. Phys.

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This paper proposes a time-domain leakage current measurement circuit that uses an external-reference-free current-to-time conversion. Our proposed current-to-time converter (CTC) utilizes a dual inverter-based conversion to provide a stable reference. We share the CTC among the devices under test (DUTs) for accurate characterization of variation. Our CTC, along with a tree-based switch structure, allows us to densely place and route the DUT transistors using a cell-based design ﬂow similar to a digital circuit design. We demonstrate our circuit by measuring subthreshold leakage currents of 256 minimum sized nMOSFETs in a 65 nm bulk low-power CMOS process. We could successfully extract the variations in subthreshold coeﬃcient and subthreshold leakage current at diﬀerent temperatures. Our circuit is also robust to supply voltage ﬂuctuation making the circuit suitable for accurate characterization of MOSFET parameters for subthreshold operation.

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Addressable test structure design enabling parallel testing of reliability devices

DeBruler

Pretti

Violette

et al. 2018

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)

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A Compact Test Structure for Characterizing Transistor Variability Beyond <inline-formula> <tex-math notation="LaTeX">$3\sigma $ </tex-math></inline-formula>

Cited by 15 publications

References 28 publications

STATE: A Test Structure for Rapid Prediction of Resistive RAM Electrical Parameter Variability

STATE: A Test Structure for Rapid Prediction of Resistive RAM Electrical Parameter Variability

On-chip leakage current variation measurement using external-reference-free current-to-time conversion for densely placed MOSFETs

Addressable test structure design enabling parallel testing of reliability devices

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