A Compact, Low-Power Analog Front-End With Event-Driven Input Biasing for High-Density Neural Recording in 22-nm FDSOI

Abstract

An ultra-small-area, low-power analog front-end (AFE) for high-density neural recording is presented in this paper. It features an 11-bit incremental delta-sigma analog-to-digital converter ( ADC) enhanced with an offset-rejecting eventdriven input biasing network. This network avoids saturation of the ADC input caused by leakage of the input-coupling capacitor implemented in an advanced technology node. Combining ACcoupling with direct data conversion, the proposed AFE can tolerate a rail-to-rail electrode offset and achieves a good trade-off between power, noise, bandwidth, input impedance, and area. Fabricated in a 22-nm fully-depleted silicon on insulator (FDSOI) process, the design occupies an active area of <0.001 mm 2 , the smallest obtained to this date for a neural AFE, and consumes <3 W from a 0.8-V supply. It achieves an input-referred noise of 11.3 Vrms in the action potential band (300 Hz -10 kHz) and 10 Vrms in the local field potential band (1 Hz -300 Hz).

A Capacitive-Feedback Amplifier with 0.1% THD and 1.18 μVrms Noise for ECG Recording

“…and the second-stage DC gain is A V2 = −g m9 • R eq2 . After simplification, the transfer function can be easily obtained as shown in (17). It can be seen that the OTA has two poles within the concerned frequency range.…”

“…In addition, some designs use an additional DC servo loop (DSL) to suppress the electrode DC offset (EDO), which can be achieved in various ways. Work [16] uses an analog integrator to achieve this, work [17] uses IDAC, which relies on an analog-to-digital converter (ADC) to achieve it, and work [18] adds a digital loop on top of the analog integrator to further improve the suppression of the DC offset. Many designs use the combination of these techniques to achieve low noise, high linearity, and low power consumption in the design of biomedical signal amplifiers [12][13][14][19][20][21].…”

Design of CMOS Circuits for Electrophysiology

“…For neural recording in the absence of artifacts, a moderate-resolution ADC (∼8-11 bits) can be employed to directly digitize the raw neural signals in a very area-and power-efficient manner, while the large EDOs can be either compensated by a mixed-signal DSL [34] or filtered out by conventional AC-coupling [38], [41], as shown in Fig. 12 (a) and 12(b).…”

“…The penalty is the required large-area coupling capacitors. This claim, however, has been challenged in some recent designs [38], [41]. This is because the capacitor can be designed reasonably small via proper engineering, and its density increases with technology scaling as more metal layers are available and the spacing between two adjacent metal tracks becomes narrower.…”

“…Additionally, the AC-coupling capacitor can be stacked above the active circuits for further area saving. At the same time, the drawbacks associated with the pseudo-resistor biasing can be avoided by periodically resetting the OTA input to its common mode [53], [57], applying a reset when the OTA input drifts outside the linear input range of the ADC [38], or resetting via the incremental operation [45]. The resetinduced kT/C noise is usually not a big concern since it gets averaged and becomes negligible compared to the overall ADC input-referred noise due to the very infrequent reset operation [38], or converted into out-of-band chopper ripple and then filtered out by the subsequent integrator [45].…”