A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs

Sharifkhani, Mohammad; Rahiminejad, Ehsan; Jahinuzzaman, Shah M.; Sachdev, Manoj

doi:10.1109/tvlsi.2009.2039949

Cited by 26 publications

(12 citation statements)

References 14 publications

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“…The curves in Fig. 6 a show that the proposed VSA allows T ACC values about five times lower than the hybrid solution in [4] and is tolerant to V OS values in the larger range [0, 100 mV]. Fig.…”

Section: Resultsmentioning

confidence: 97%

“…6c prove that energy is quite insensitive to T ACC . In Table 1, principal results of 180 and 90 nm technologies are compared with the most recent schemes in [3][4][5] and the much shrunk 22 nm solution in [7]. Conclusions: This design study shows that the proposed offset-tolerant VSA has a noteworthy potential in reducing the offset problem and the sense delay, given by the summation of T ACC , T INV and pre-charging time.…”

Section: Circuit Description and Operationmentioning

confidence: 92%

“…In addition, current sense amplifiers have shown limitations in practical applications where the supposed advantages, mainly due to the requirement of reduced voltage swing, are often compensated by the requirement of a large trans-impedance amplification. Therefore, two-stage hybrid current-voltage solutions have been proposed [4,5] with increased number of devices and power consumption as well as reduced velocity. In order to exploit the compactness of voltage sense amplifier (VSA) topologies and their good sensing velocity, in this paper the design of a new VSA bit-line sensing circuit is presented, which combines offset cancellation and compensation schemes.…”

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confidence: 99%

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Design of an offset‐tolerant voltage sense amplifier bit‐line sensing circuit for SRAM memories

et al. 2016

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The design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset cancellation and compensation solutions. FCMOS inverters, brought to operate in their maximum gain region, are used to compensate the systematic offset of the sense amplifier and reduce the sensing delay. Systematic offset of the inverter amplifiers is cancelled by means of equalising feedback connections. A simulation analysis in Cadence environment and TSMC PDK demonstrates the very good potential of the proposed solution when it is compared with the recent and the established literature

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Section: Resultsmentioning

confidence: 97%

Section: Circuit Description and Operationmentioning

confidence: 92%

mentioning

confidence: 99%

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Design of an offset‐tolerant voltage sense amplifier bit‐line sensing circuit for SRAM memories

et al. 2016

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“…Cascodecurrent-load CSAs (CCL-CSAs), [24][25], require long BL settling times and have a small 1st-stage voltage difference when reading a small cell current (I CELL ). Hybrid SAs [26][27] have small differential voltage on the data-lines (DLs) when reading a small I CELL . Current-mirror CSA (CM-CSA) [28][29] has fast read speed but cannot sense small I CELL , due to mismatch in the mirror-stage device.…”

Section: Introductionmentioning

confidence: 99%

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

Vishvakarma

Reniwal

Khuswah

et al. 2015

2015 IEEE International Symposium on Nanoelectronic and Information Systems

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The importance of embedded memory in contemporary multi-core processors and system-on-chip (SoC) for wearable electronics and IoT applications is growing. Intensive data processing in such processors and SoCs necessitates larger on-chip, energy-efficient static random access memory (SRAM). However, there are several challenges associated with low-voltage SRAMs. In this paper we have discussed the major hurdles at technology front for low power and robust SRAM design. We have discussed the different circuit techniques to mitigate these severe reliability concerns for embedded SRAM. Furthermore, this paper presented the recent development in embedded memory technology targeted to efficient computation. We have analyzed the effect of various device sizing on memory stability. The novel current mode circuit is also presented for high speed, offset tolerant SRAM sense amplifier. The FinFET memory design is explored to reduce the external manifestation of device mismatch on SRAM stability and memory yield.Keywords-Current Latch Sense Amplifier, Offset, SRAM, inter die variations, intra die variations.

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“…Additional switches and amplifiers are usually placed in a feedback loop at the expense of complexity, area, and power to improve the speed [7]. Current, voltage sense amplification has proven to be an effective way to overcome these barriers [8]. This paper presents a thorough analysis for the proposed current/voltage sense amplifier structure with offset cancellation.…”

Section: Introductionmentioning

confidence: 99%

A scalable offset-cancelled current/voltage sense amplifier

Attarzadeh

Sharifkhani

Jahinuzzaman

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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the application of current sense amplifiers in scaled SRAM design is limited by two factors: the DC offset due to the device mismatch and limited voltage headroom. The presented scheme reduces the effect of offset by proposing an extra phase for offset cancellation before current sensing takes place. A twofold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. The offset cancellation phase takes place in parallel to the wordline decoding time in order to speed up the current sensing. The proposed scheme requires a small power budget due to a self shut off mechanism. In addition to presenting a comparison with the conventional schemes, the efficiency of the proposed scheme is evaluated in 90nm, 130nm and 180nm CMOS technologies to show the scalability and the robustness of the proposed scheme under smaller voltage headroom. I.978-1-4244-5309-2/10/$26.00 ©2010 IEEE

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A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs

Cited by 26 publications

References 14 publications

Design of an offset‐tolerant voltage sense amplifier bit‐line sensing circuit for SRAM memories

Design of an offset‐tolerant voltage sense amplifier bit‐line sensing circuit for SRAM memories

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

A scalable offset-cancelled current/voltage sense amplifier

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