A compact explicit DC model for short channel Gate-All-Around junctionless MOSFETs

Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors

“…The expression of drain current is free of any fitting parameters and can be evaluated based on the physical device parameters such as that of geometry and doping. Additionally, short channel effects were also taken into account considering velocity saturation, an effective mobility, µeff, and incorporating an effective gate length, Leff=L-ΔL, where L is the physical device gate length and ΔL is calculated following [9], (4) With, vsat being the saturation velocity and S being a parameter ensuring that ΔL tends to zero below the threshold, defined as [9], (5) Where QDP0+QC0 is the total mobile charge at the source, given by the long channel expression and B is a smoothing parameter. Furthermore, the short channel corrections incorporates an effective drain voltage, Vdeff, through (4) that reaches its maximum at VSAT, the saturation voltage [9], (6) Here, A2 is another smoothing parameter for the transition of the drain voltage to VSAT.…”

“…Additionally, short channel effects were also taken into account considering velocity saturation, an effective mobility, µeff, and incorporating an effective gate length, Leff=L-ΔL, where L is the physical device gate length and ΔL is calculated following [9], (4) With, vsat being the saturation velocity and S being a parameter ensuring that ΔL tends to zero below the threshold, defined as [9], (5) Where QDP0+QC0 is the total mobile charge at the source, given by the long channel expression and B is a smoothing parameter. Furthermore, the short channel corrections incorporates an effective drain voltage, Vdeff, through (4) that reaches its maximum at VSAT, the saturation voltage [9], (6) Here, A2 is another smoothing parameter for the transition of the drain voltage to VSAT. Considering that the source and drain access region resistances degrade the drain current above threshold, the final expression of the drain current can be written as a function of the long channel current (IDS,0), using (3), taking into account the corrections due to short-channel effects described by equations ( 4)-( 6), as follows [9], (7) Here, RS and RD are the source and drain series access resistances, respectively; NF is the number of nanowires in parallel, η1 is a fine tuning parameter to take into account the drain-voltage dependence of the series access resistances and QDP,Vdeff+QC,Vdeff is the total mobile charge at the drain end (pinch-off) of the channel.…”

“…Furthermore, the short channel corrections incorporates an effective drain voltage, Vdeff, through (4) that reaches its maximum at VSAT, the saturation voltage [9], (6) Here, A2 is another smoothing parameter for the transition of the drain voltage to VSAT. Considering that the source and drain access region resistances degrade the drain current above threshold, the final expression of the drain current can be written as a function of the long channel current (IDS,0), using (3), taking into account the corrections due to short-channel effects described by equations ( 4)-( 6), as follows [9], (7) Here, RS and RD are the source and drain series access resistances, respectively; NF is the number of nanowires in parallel, η1 is a fine tuning parameter to take into account the drain-voltage dependence of the series access resistances and QDP,Vdeff+QC,Vdeff is the total mobile charge at the drain end (pinch-off) of the channel.…”

“…Consequently, thermionic (Ith), tunneling (Itun) and bandto-band tunneling (BTBT) contributions through gateinduced drain leakage (GIDL) are added as separate branch currents [10] to the total drain current, in order to model the subthreshold behavior of the drain current. The expression used in the compact model for the BTBT current at the drain end reads [10], (8) With LAccess being the lengths of the source and drain access regions outside the channel, BGIDL is a physics based parameter with a theoretical value of 21.3 MV/cm [10] and Esegd is the electric field in the drain overlap region, given as, (9) Here, Vsegd is the gate-drain voltages across the oxide and AGIDL, CGIDL are two GIDL fitting parameters.…”

Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

“…Moreover, due to high channel doping the mobility reduces due to ionization scattering and subsequently results in lower transconductance [6] [7] . To overcome these challenges, many authors have introducing solutions such as junctionless nanowire transistor with a dual material gate [8] , dual material gate junctionless transistor with high-k spacer [9] , dual material gate silicon on nothing junctionless transistor [10] , dual material double gate junctionless transistor considering fringing field [11] , charge plasma based transistor with induced graded channel [12] , gate-all-around junctionless transistor [13] , non-uniformly doped symmetric double gate junctionless transistor [14] , have been proposed. Among these junctionless transistor and architecture, dual material double gate junctionless transistor is best candidate for CMOS logic circuits [15] .…”