A Compact Approach to On-Chip Interconnect Heat Conduction Modeling Using the Finite Element Method

Abstract

Over upcoming electronics technology nodes, shrinking feature sizes of on-chip interconnects and correspondingly higher current densities are expected to result in higher temperatures due to self-heating. This study describes a finite element based compact thermal modeling approach to investigate the effects of Joule heating on complex interconnect structures. In this method, interconnect cross section is assumed to be isothermal and conduction along the interconnect is retained. A composite finite element containing both metal and dielectric regions is used to discretize the interconnect stack. The compact approach predicts the maximum temperature rise in the metal to within 5–10% of the detailed numerical computations, while requiring only a fraction of elements. Computational time for the compact model solution is several seconds, versus many hours for the detailed solutions obtained through successive mesh refinement until grid independence is achieved. For a comparable number of elements, the compact model is in general much more accurate than the traditional finite element approach. To validate the simulations, temperature rise in a 500-link two-layer interconnect with a via layer was measured at several current densities. The compact method predicts the temperature rise of the 500-link chain to within 5% of the measurements thereby validating the method. The approach described here could be an efficient technique for full chip Joule heating simulations and for clock signal propagation simulations, which are performed as part of designing next generation chip architectures.

Electromigration-Induced Plastic Deformation in Cu Interconnects: Effects on Current Density Exponent, n, and Implications for EM Reliability Assessment

“…In the absence of extreme local instabilities (such as hot spots or local meltdown due to current-crowding effects, for instance), the effect of Joule heating is predicted to be merely a rise of between 5% and 10% at high j compared with at low j in the global temperature of the interconnect lines. [20][21][22][23][24][25] This is insufficient to cause a large drop in MTF at high j that would be required to cause n to deviate significantly from 1. This is especially true for the case of the Cu-SiO 2 interconnect scheme, such as used in the present study, due to the high thermal conductivity of SiO 2 .…”

Characterization of steady and transient heating of interconnects - a review

“…They showed that with a reduction in mesh size, shorter simulation times can be achieved. Compact thermal models for on-chip interconnect heating analysis have also been developed [41][42]. The threedimensional compact finite element modeling of interconnects with vias by Gurrum et al [42] is briefly explained.…”

“…In the compact approach, investigated by Gurrum et al [42] , a given element is permitted to have both metal and dielectric regions. This will reduce the number of nodes at which temperature needs to be computed.…”

Generalized Heat Transition Matrix for Arbitrarily Shaped Thermal Media and Its Applications to Steady-State Heat Conduction Problems in Large-Scale Systems

“…In practical engineering, heat transfer analysis of multiscale thermal systems, such as system-on-package (SOP) [1] and other electronic systems [2,3], is an important issue. On one hand, these systems usually consist of many different modules, and each module may have very fine internal structure; on the other hand, the heat sources distributed in modules are spatial functions of electric fields or current densities.…”