A Compact Analytical Model for 2D Triple Material Surrounding Gate Nanowire Tunnel Field Effect Transistors

Saraswathi, D.; Balamurugan, N. B.; Priya, G. Lakshmi; Manikandan, S.

doi:10.1007/978-81-322-2268-2_35

Cited by 10 publications

(5 citation statements)

References 2 publications

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“…The bitlines have a high value of the capacitive load, which in turn offers RC delays. The recent SRAM designs [ 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ] reported depict the novel device architectures of 6T SRAM with FinFET, Memristor, and Junctionless TFETs, to claim it to be a low-power device. Here, with our proposed sense amplifier design, the power reduction techniques like negative wordline and source biasing were combined and utilized.…”

Section: Proposed Sense Amplifier: Results and Discussionmentioning

confidence: 99%

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

et al. 2023

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We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

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Section: Proposed Sense Amplifier: Results and Discussionmentioning

confidence: 99%

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

et al. 2023

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“…In scenarios where the work function of the gate metal on the drain side is lower in comparison to the source side (Case 3 and Case 4), a significant decrease in the peak electric field occurs at the drain side. 74 This reduction effectively mitigates short channel effects, such as Drain-Induced Barrier Lowering (DIBL), leading to a decreased I OFF current and an enhanced I ON -to-I OFF current ratio. 74,75 Table V presents the threshold voltage sensitivity (S Vth ) and current sensitivity (S ID ) values for various biomolecules as the temperature is varied from T = 200 kelvin to T = 400 kelvin.…”

Section: Vth Th No Biomolecule Thwith Biomoleculesmentioning

confidence: 99%

“…74 This reduction effectively mitigates short channel effects, such as Drain-Induced Barrier Lowering (DIBL), leading to a decreased I OFF current and an enhanced I ON -to-I OFF current ratio. 74,75 Table V presents the threshold voltage sensitivity (S Vth ) and current sensitivity (S ID ) values for various biomolecules as the temperature is varied from T = 200 kelvin to T = 400 kelvin. High temperatures result in the formation of a larger number of charge carriers, so the same drain current can now be attained at a lower V GS , leading to a decrease in threshold voltage.…”

Section: Vth Th No Biomolecule Thwith Biomoleculesmentioning

confidence: 99%

Dielectrically-Modulated GANFET Biosensor for Label-Free Detection of DNA and Avian Influenza Virus: Proposal and Modeling

Yadav,

Das,

Rewari

2024

ECS J. Solid State Sci. Technol.

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This paper introduces a novel device called the gate all around engineered gallium nitride field effect transistor (GAAE-GANFET), designed specifically for label-free biosensing applications. This innovative gate-all-around engineering in GANFET integrates various device engineering techniques, such as channel engineering, gate engineering, and oxide engineering, to enhance biosensing performance. The channel engineering techniques refer to the use of a gallium nitride channel with a step-graded doping profile, divided into three distinct regions. In contrast, the gate engineering technique refers to the cylindrical split-gate-underlap architecture. The oxide engineering technique involves stacking Al2O3 and HfO2. Moreover, this biosensor incorporates two-sided gate underlap cavities that facilitate the immobilization of biomolecules. These open cavities not only provide structural stability but also simplify the fabrication process to a significant extent. The viability of this biosensor as a label-free biosensor has been evaluated using an antigen and an antibody from the Avian Influenza virus and DNA as the target biomolecules. The proposed analytical model and TCAD simulation results are in excellent agreement, demonstrating the reliability of the proposed device. Additionally, the biosensor's sensitivity, which depends on cavity length, doping concentration, gate metal work function, and temperature variation, has been thoroughly explored.

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“…It is based on Moore’s law, which stipulates that every two years the count of transistors on a particular region of silicon becomes twice. FinFET’s appeal stems from its lower leakage current, higher performance, and a variety of implementation techniques including the usage of Tunnel FETs and Junctionless Tunnel FETs were also used in the literature for the SRAM design [ 8 , 9 , 10 , 11 ]. Scaling down, according to Moore’s law, provides a high integration density on the chip and aids in the management of the short channel effect.…”

Section: Implementation Of 6t-sram Using Cmos Finfet and Memristormentioning

confidence: 99%

“…The value of ‘q’ is calculated with the use of a sensory amplifier. To save the new value in the SRAM cell, the device must be set to “write mode” [ 8 , 9 ]. Changes to the SRAM cell are stored in advance when ‘q’ is set to zero or one.…”

Section: Implementation Of 6t-sram Using Cmos Finfet and Memristormentioning

confidence: 99%

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

et al. 2023

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Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

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A Compact Analytical Model for 2D Triple Material Surrounding Gate Nanowire Tunnel Field Effect Transistors

Cited by 10 publications

References 2 publications

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

Dielectrically-Modulated GANFET Biosensor for Label-Free Detection of DNA and Avian Influenza Virus: Proposal and Modeling

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

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