A collaborative optimization for floorplanning and pin assignment of 3D ICs based on GA-SA algorithm

Qin, He; Zhang, Mu-Shui

doi:10.1109/emcsi38923.2020.9191559

Cited by 4 publications

(4 citation statements)

References 6 publications

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“…Various algorithms exist to group and slice up the cell into the gate level net-list according to parameters such as maximum interconnect length and logical depth. One such algorithm is the Genetic and Simulated Annealing (GSA) algorithm [25], which is used to define weight values for different cells while clustering them to perform efficient placement. The macro placement has further been explored as a fully automated solution using machine learning models in [26].…”

Section: Literature Reviewmentioning

confidence: 99%

PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories

Fadnavis¹,

B.S²

2021

IJATEE

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The large-scale growth of the electronics industry in the past decade has led to small-sized gadgets flooding the market. Initially, only Personal Computers (PC) employed the use of multi-core processing, however, now even small hand-held gadgets have come to possess similar computational power as the PC and laptop. With mobile manufacturers opting for multicore processing and graphics -intensive application usage, memory storage and access has become a crucial aspect to achieve high performance.

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Section: Literature Reviewmentioning

confidence: 99%

PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories

Fadnavis¹,

B.S²

2021

IJATEE

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“…The pin assignment is one of the most important problems to reduce wirelength meanwhile optimizing both critical delay and power consumption in M3D integration [5], [6]. Previously, the pin assignment in M3D has been optimized by simultaneous optimization of pin assignment, TSV placement [8], and genetic and simulated annealing algorithm to co-optimize area, wirelength, and temperature [9].…”

Section: Related Workmentioning

confidence: 99%

“…By formulating the problem as a min-cost multi-commodity flow model, they have improved the total wirelength of the target design by 38%. Hu et al [9] has proposed Genetic and Simulated Annealing (GA-SA) algorithm to find the optimal 3D IC floorplanning and assignments of on-chip and I/O package pins considering area, interconnection length, maximum temperature and inductance of pins of the design.…”

Section: Related Workmentioning

confidence: 99%

An Effective Block Pin Assignment Approach for Block-Level Monolithic 3-D ICs

Kim

Yoon

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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In a 2D design, the block pins are located at the periphery of a block optimally since blocks are placed side-byside horizontally in a single placement layer. However, Monolithic 3D (M3D) integration relieves this boundary constraint by allowing vertical block communication between different tiers based on a nm-scale pitch of 3D interconnection. In this article, we present a design methodology named Pin-in-the-Area that assigns block pins at any position inside the boundary of a block using commercial 2D P&R tools, and enables an efficient block implementation and integration for a block-level M3D ICs. Our Pin-in-the-Area starts from the netlist restructuring and connectivity-aware tier-by-tier chip planning, which define blocks and decide their sizes and (X, Y, Z) locations for a two-tier M3D design. Next, we perform wirelength-driven 3D placement to minimize 3D half-perimeter wirelength and find optimal pin locations inside the boundary of a block. Once block designs are done, we apply the unique macro handling scheme to the top-level timing closure. Based on a 28nm two-tier M3D hierarchical design result, we show that our solution offers 13.6% and 24.7% energy-delay-product reduction compared to the M3D design with pins assigned at the block boundaries and its 2D counterpart, respectively. Index Terms-3D integrated circuits, physical design (EDA), block-level design, block pin assignment, Pin-in-the-Area.

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“…Therefore, we propose an improved PIO algorithm, called improved Metropolis criterion PIO (IMCPIO), inspired by the simulated annealing (SA) algorithm [7] and the Iterative Modified PSO (IMPSO) algorithm. The IMPIO algorithm has the following advantages over the basic PIO algorithm: (1) It allows inferior solutions to be accepted with a certain probability, which enables the algorithm to escape local optima and enhances its robustness; (2) It introduces a temperature parameter T, which decreases gradually.…”

Section: Introductionmentioning

confidence: 99%

Metropolis criterion pigeon-inspired optimization for multi-UAV swarm controller

Guan,

Cheng

2024

Intelligence & Robotics

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This paper presents a new multiple unmanned aerial vehicle swarm controller based on Metropolis criterion. This paper presents the design of a controller, utilizing the improved Metropolis criterion pigeon-inspired optimization (IMCPIO) and proportional-integrational-derivative (PID) algorithms, and conducts comparative experiments. Simulation outcomes demonstrate the enhanced performance of the multi-unmanned aerial vehicle formation controller, which is based on IMCPIO, when compared to the basic pigeon-inspired optimization (PIO) algorithm and the genetic algorithm. The IMCPIO algorithm for the energy difference discrimination makes it a faster convergence and more stable effective optimization. Hence, the controller introduced in this study proves to be both practical and resilient.

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A collaborative optimization for floorplanning and pin assignment of 3D ICs based on GA-SA algorithm

Cited by 4 publications

References 6 publications

PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories

PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories

An Effective Block Pin Assignment Approach for Block-Level Monolithic 3-D ICs

Metropolis criterion pigeon-inspired optimization for multi-UAV swarm controller

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