A code-generator generator for multi-output instructions

Abstract

We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very common in the area of Application Specific Instruction Set Processors (ASIPs) and Digital Signal Processors (DSPs) which are frequently used in Systemon-Chips as programmable cores. In order to provide high-level programmability, and consequently guarantee widespread acceptance, sophisticated compiler support for these programmable cores is of high importance. Since it is not possible to model MultiOutput Instructions as trees in the compiler's Intermediate Representation (IR), traditional approaches for code selection are not sufficient. Extending traditional code-generation approaches for MOI-selection is essentially a graph covering problem, which is known to be NP-complete. We present a new heuristic algorithm incorporated in a retargetable code-generator generator capable of exploiting arbitrary inherently parallel MOIs. We prove the concept by integrating the tool into the LCC compiler which has been targeted towards different Instruction Set Architectures based on the MIPS architecture. Several network applications as well as some DSP benchmarks were compiled and evaluated to obtain results.

Instruction Selection

“…My tentative guess is that BURG was derived from the BURS acronym and stands for Bottom-Up Rewrite Generator. 10 During my research for this book, I came across the following systems, all with equally creative naming schemes: BURG [138], CBURG [303], DBURG [117], GBURG [139], GPBURG [162], HBURG [48], IBURG [137], JBURG [171], LBURG [169], MBURG [160,161], WBURG [285], and OCAMLBURG [238]. some combination of states, including the state that was just popped.…”

“…In 2007, Scharwaechter et al [303] introduced what appears to be the first instruction selection technique to use the MWIS approach for selecting patterns. But despite this novelty, the most cited contribution of their design is its extensions to instruction set grammars to support multi-output instructions.…”

“…A generic subgraph isomorphism algorithm is used to find all matchsets, and pattern selection is then modeled as an instance of the CP model with the additional constraints to schedule the subinstructions such that they can be replaced by the original disjoint-output instruction. Arslan and Kuchcinski's design therefore differs from the previous techniques that we have seen before, where matches of partial patterns are recombined into matches of complex patterns prior to pattern selection (see for example Scharwaechter et al [303], Ahn et al [2], Arnold and Corporaal [25,26,27]), as it allows these two problems to be solved in tandem. The design is also capable of accepting multiple, disconnected program DAGs as a single input.…”

“…Ebner et al first extended the grammar to allow rules to contain multiple productions in a similar fashion to that of Scharwaechter et al [303] (see Chapter 4, p. 89). We will refer to such rules as complex rules, and the productions within a complex rule will be called proxy rules.…”

Compiling for automatically generated instruction set extensions

“…Scharwaechter et al [18] continue the development of complex instruction mappers by extending the idea of a code-generator generator to be able to handle parallel instructions. The extended generator represents basic blocks and instructions as directed acyclic graphs (DAGs).…”