A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor

Abstract

With the increasing energy-efficiency requirements for the edge computing platforms, the Instruction Set Architecture (ISA) design and precision tuning techniques highlight the possibility of improving the efficiency of dedicated operations. RISC-V as an open-source instruction set shows excellent application potential. On the other hand, the modular ISA design brings elegant design ideas, and designers can pay more attention to the collaborative design of essential ISA and software libraries. To support the design of efficient precision tuned applications, this paper presents some novel architecture and software co-design based on integer and fixed-point computations. Based on a collection of RISC-V instruction custom designs for a fixed-point mathematics library, we propose an optimal decisionmaking methodology for the customized ISA design space exploration to optimize some dedicated algorithms.

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

“…(utilization) columns of Table 1. To underscore the versatility of the GPU acceleration framework in handling very large-scale netlisting circuits, we conducted a methodology validation using a million-gate scale System-on-Chip (SoC) netlisting, specifically BJUT-RISC [36]. Table 2 details the FPGA resource overhead statistics, with the utilization rate of LUTs exceeding 90%.…”

Clock Mesh Synthesis Methodology Based on Combinatorial Optimization

“…Therefore, we can set weight values for different emphasis requirements, and the physical layout process also verifies the feasibility of the proposed methodology. In order to further verify the effectiveness of the design method applied to the physical layout (IP modules that have been taped) [28][29][30], we conducted an experimental comparison with a commercial EDA tool flow, where the commercial EDA tool flow is a fully automatic clock tree synthesis method. Based on the proposed clock mesh design method, we optimized the experimental results through a fine-tuning hierarchical clock network.…”