A CMOS up-conversion receiver front-end for cable and terrestrial DTV applications

Retz, G.; Burton, Patrick D.

doi:10.1109/isscc.2003.1234378

Cited by 29 publications

(12 citation statements)

References 2 publications

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“…In the first stage, to attain a large gain range, a resistive attenuator is used. Previous variable gain amplifiers have used a single amplifier with switches [16] or multiple amplifiers without switches [5], [17]. The first one requires an input switch even at the highest gain mode, which results in degradation of the NF.…”

Section: Rf Pga Architecturementioning

confidence: 99%

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A 13-dB IIP3 Improved Low-Power CMOS RF Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV Applications

Kim¹,

Kim²

2006

IEEE J. Solid-State Circuits

103

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A CMOS RF digitally programmable gain amplifier (RF PGA), covering various terrestrial mobile digital TV standards (DMB, ISDB-T, and DVB-H) is implemented as a part of a low-IF tuner IC using 0.18-m CMOS technology. An improvement of 13-dB IIP3 is attained without significant degradation of other performance criteria like gain, noise figure, common-mode rejection ratio, etc., at similar power consumption. This is achieved by applying a newly proposed differential circuit gm (the second derivatives of transconductance) cancellation technique, called the differential multiple gated transistor (DMGTR). In the DMGTR amplifier, the negative value of gm in the fully differential amplifier can be compensated by the positive value of gm in the pseudo differential amplifier which is properly sized and biased. By adopting the DMGTR, a low-power highly linear RF PGA is implemented. Also, in order to have wide gain range with fine step resolution, a new RF PGA architecture is proposed. The measurement results of the proposed RF PGA exhibit 50-dB gain range with 0.25-dB resolution, 4.5-dB noise figure, a 4-dBm IIP3 (maximum 30 dBm) and 25-dB gain at 16-mW power consumption.

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Section: Rf Pga Architecturementioning

confidence: 99%

“…Thus, it is important to have a high rejection to digital circuitry noise, and maximize linearity/(power consumption). Also, a large gain range with fine resolution and a low noise figure (NF) in an RF domain, are still challenging on a single CMOS substrate [5].…”

mentioning

confidence: 99%

A 13-dB IIP3 Improved Low-Power CMOS RF Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV Applications

Kim¹,

Kim²

2006

IEEE J. Solid-State Circuits

103

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“…The up-conversion receiver front-end usually consists of a wideband low noise amplifier (LNA) and an up-conversion mixer. In previously published works in [1,2,3,4,5,6,7,8,9], all of them adopted the Gilbert double-balanced active mixer with LC tank load. The impedance of LC tank load was matched to the termination impedance of SAW BPF.…”

Section: Introductionmentioning

confidence: 99%

“…Concerning a wideband LNA, various topologies such as cascoded and degenerated differential-pair LNA in [1] and [3], shunt feedback LNA in [2], [5] and [6], common gate-common source (CG-CS) balun LNA in [4], and noise canceling capacitively cross-coupled (CCC) CG LNA in [9] and [10] have been devised for DTV applications. Among them, the noise canceling LNA involving a CG amplifier and a CS amplifier like those in [9] and [10] is suitable for the passive mixer-based up-conversion receiver front-end because it can directly drive low impedance load without requiring additional inter-stage buffer.…”

Section: Introductionmentioning

confidence: 99%

An up-conversion TV receiver front-end with noise canceling body-driven pMOS common gate LNA and <i>LC</i>-loaded passive mixer

Nam

2017

IEICE Electron. Express

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A low noise and highly linear up-conversion digital TV (DTV) receiver front-end, which consists of a noise canceling body-driven pMOS common gate (CG) LNA, a LC-loaded passive mixer, and a surface acoustic wave (SAW) driver, is implemented in a 0.18 µm CMOS process. The pMOS input stage and body-driven technique in the conventional noise canceling capacitively cross-coupled (CCC) CG LNA greatly improve noise figure (NF) over DTV frequency band without extra power consumption. The linearity of the proposed up-conversion LC-loaded passive mixer and modified source follower-based SAW driver is high enough to handle strong blockers without suffering from desensitization. The designed RF front-end shows a measured conversion gain of greater than 17 dB, a NF of less than 2.7 dB, and a third-order input-referred intercept point (IIP3) of greater than −2.7 dBm over DTV frequency band. The power consumption of the proposed RF front-end is 70 mW at a 1.8 V supply voltage.

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“…DVB-H technology adapts the digital video broadcasting-terrestrial (DVB-T) system for digital terrestrial television, to the specific requirements of handheld, battery-powered receivers. DVB-H can offer a downstream channel at high data rates which can be used standalone or as an enhancement of mobile telecoms networks which many typical handheld terminals are able to access anyway [1,2]. This paper deals with the design of the RF and mixed signal part of a DVB-H receiver for the UHF band.…”

Section: Introductionmentioning

confidence: 99%

RF and mixed signal circuits for a DVB-H receiver

Khemchandani

Pino

López-Morillo

et al. 2010

Analog Integr Circ Sig Process

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This paper presents a tutorial on RF and mixed signal circuits design for a digital video broadcastinghandheld tuner. A detailed description of the wideband low noise amplifier, the mixer, the synthesizer and the ADC, which are the most challenging components of a receiver, are carried out. Requirements relative to frequency range, sensitivity, noise figure, linearity, phase noise gain and dynamic range are discussed. The LNA uses a cascode configuration, combining a resistive loaded LNA with a conventional resistive shunt-feedback, in order to achieve a low power, low noise and wide bandwidth. The mixer uses a classical Gilbert cell configuration. The VCO employs techniques like emitter degeneration, capacitor divider, and optimum bias for minimum noise to improve phase noise requirements and oscillation amplitude. There are two ADC structures, one of which is a delta sigma ADC. The blocks are implemented in a AMS 0.35 lm BiCMOS process.

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A CMOS up-conversion receiver front-end for cable and terrestrial DTV applications

Cited by 29 publications

References 2 publications

A 13-dB IIP3 Improved Low-Power CMOS RF Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV Applications

A 13-dB IIP3 Improved Low-Power CMOS RF Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV Applications

An up-conversion TV receiver front-end with noise canceling body-driven pMOS common gate LNA and <i>LC</i>-loaded passive mixer

RF and mixed signal circuits for a DVB-H receiver

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