2018
DOI: 10.1109/tcsi.2018.2853649
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A CMOS Temperature Sensor With Versatile Readout Scheme and High Accuracy for Multi-Sensor Systems

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Cited by 29 publications
(12 citation statements)
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“…configuration, especially the V BE gain (e.g., α in [19]), it is still beneficial if we can minimize the number of V BE sampling in one temperature conversion to reduce the total noise sampled from the sensor frontend, especially for lowpower high-resolution sensors. With this consideration, this work digitizes the ratio Z T = k • V BE /V BE as it does not sample V BE in every clock cycle, with k being a gain factor to accommodate for the readout dynamic range [11], [21]. k (set to be 3 or 6 in this work) is smaller than α (=16) in [19] or V BE /V BE max (=28) in the zoom ADC readout [20].…”
Section: B Sensor Readout Selectionmentioning
confidence: 99%
“…configuration, especially the V BE gain (e.g., α in [19]), it is still beneficial if we can minimize the number of V BE sampling in one temperature conversion to reduce the total noise sampled from the sensor frontend, especially for lowpower high-resolution sensors. With this consideration, this work digitizes the ratio Z T = k • V BE /V BE as it does not sample V BE in every clock cycle, with k being a gain factor to accommodate for the readout dynamic range [11], [21]. k (set to be 3 or 6 in this work) is smaller than α (=16) in [19] or V BE /V BE max (=28) in the zoom ADC readout [20].…”
Section: B Sensor Readout Selectionmentioning
confidence: 99%
“…In order to realize the gain factor = 3, the differential input voltage of the ADC applies the following sequence of voltages: + , − , + , when BS = 1 and + , − , + , 0 when BS = 0. As shown in Figure 6 , a cascade-of-integrators feedforward form (CIFF) structure was used because the feedforward structure reduces the output swing in each stage, so it is easy to meet integrators’ linearity and slewing requirements [ 17 ]. The input of the second-order incremental - ADC changes corresponding to the bit-stream.…”
Section: Readout Circuitmentioning
confidence: 99%
“…Using two sampling capacitors in the proposed ADC requires a different charge-balancing scheme than that of the zoom-ADC. Similar to [20], the ADC digitizes the ratio Y T = 3 • ∆V BE /V BE2 , which varies from 0.15 to 0.72 as T die varies from −40 • C to +180 • C. The factor of 3 was chosen to maximize the ADC's dynamic range in this temperature range.…”
Section: B Charge-balancing Scheme In the Low-leakage Adcmentioning
confidence: 99%