A CMOS Power Amplifier With a Built-In RF Predistorter for Handset Applications

Son, Ki Yong; Koo, Bonhoon; Hong, Songcheol

doi:10.1109/tmtt.2012.2198230

Cited by 32 publications

(8 citation statements)

References 41 publications

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“…The proposed DCOC DVGA can be directly interfaced to a digital baseband without the need of a digital to analog converter (DAC). The DAC significantly complicates the design and also increases the DC power consumption [17]. In addition, the proposed DVGA has a differential DCOC at the output of the VGA core based on a passive low-loss RC-HPF that takes stability into consideration by avoiding any feedback or feed-forward loops along the signal path and improves the DVGA settling time.…”

Section: Design Topologymentioning

confidence: 99%

Temperature-Compensated dB-linear Digitally Controlled Variable Gain Amplifier With DC Offset Cancellation

Kumar

Yeo

2013

IEEE Trans. Microwave Theory Techn.

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This paper presents a compact digitally controlled variable gain amplifier (DVGA) with capabilities of both temperature compensated linear-in-decibel (dB-linear) gain control and DC offset cancellation (DCOC) without making use of either the feedback or the feed-forward loop. The proposed DVGA design is a 3 stage inductorless cascaded amplifier that is integrated with a temperature compensated dB-linear gain control, a DCOC, an output common mode feedback (CMFB), a 6-bit digital gain control (with a 64 step resolution), a power shutdown mode, and a linearizer for improving the 1-dB gain compression point. The design is fabricated using a commercial 0.18-m SiGe BiCMOS technology. The DVGA has a measured gain range of 18.4 dB with an average step size of 0.3 dB, a 3-dB bandwidth from 2 MHz to 1.9 GHz with a ±0.75 dB gain flatness from 2.75 MHz to 1.2 GHz, an input 1-dB gain compression point better than -12.5 dBm, an input return loss better than 12 dB, an output return loss better than 16 dB, and a DC power consumption of 12.2 mW from a 1.8 V supply. The core DVGA, by excluding the I/O measurement pads, occupies a die area of 160 m x 300 m.

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Section: Design Topologymentioning

confidence: 99%

Temperature-Compensated dB-linear Digitally Controlled Variable Gain Amplifier With DC Offset Cancellation

Kumar

Yeo

2013

IEEE Trans. Microwave Theory Techn.

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“…Pre-distorter circuit cancels out the nonlinearities of PA by creating a distortion characteristic precisely opposite to that of PA. IMD products of the PA are canceled out when IMD products generated by the predistorter have exactly equal and out of phase-amplitude, which improves the overall linearity of the PA. However, additional device working as pre-distorters consumes extra power, which degrades the efficiency of the PA [18], [19].…”

Section: Introductionmentioning

confidence: 99%

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

Rawat

Rajendran

Mariappan³

et al. 2022

IEEE Access

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This paper presents a bias modulation linearization technique for a 919-923 MHz CMOS power amplifier which employs driver voltage modulation and main amplifier split bias. Through the proposed linearization technique, it is observed that the peak third-order intercept point (OIP3) across the output power is shifting according to the bias conditions of the split-bias power amplifier (SBPA). The third-order transconductance (gm3) terms are suppressed at the output by phase cancellation achieved by optimization of the bias voltages of the PA. A high dynamic range bias circuit is integrated at the driver and split main to enhance the linearity of the CMOS PA, eradicating the need for pre-distortion linearizers. The two-stage SBPA is designed and fabricated in a 180 nm CMOS process with six-metal layers and a chip size of 1.820 x 1.771 mm 2 to operate at the supply voltage of 3.3 V. The bias voltages of both driver and split main stages are varied from 0 V to 2.0 V with a linear step size of 0.2 V. The proposed SBPA delivers a saturated output power (Pout) of 27 dBm with maximum power-added efficiency (PAE) of 44.4 % and peak OIP3 of 39 dBm. A maximum linear Pout of 21 dBm with 29 % PAE is achieved at an adjacent channel leakage ratio (ACLR) of -30 dBc and 4 % error vector magnitude (EVM), satisfying the LoRa specifications.INDEX TERMS Adjacent channel leakage ratio (ACLR), bias circuit, complementary metal-oxidesemiconductor (CMOS), error vector magnitude (EVM), intermodulation distortion (IMD), long-range (LoRa), power amplifier, radio frequency power amplifier (RFPA), third-order intercept point (OIP3)

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“…However, the linearity performance of the aforementioned techniques are quite arduous to be achieved because of the requirement of complex supply modulators for envelope tracking and the precise power splitting/combining network for both the out-phasing and Doherty PA (Fang and Zhang, 2019). This motivates significant research efforts in reducing the trade-off between efficiency and linearity in CMOS PAs (Jeon et al, 2013;Son et al, 2012;Joo et al, 2013;Francois and Reynaert, 2012). For PAs, deep class-AB operation is the most convenient in terms of linearity and efficiency.…”

Section: Introductionmentioning

confidence: 99%

A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm

Mariappan

Rajendran

Noh

et al. 2021

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Purpose The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE). Design/methodology/approach The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity. Findings For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc. Originality/value In this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

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A CMOS Power Amplifier With a Built-In RF Predistorter for Handset Applications

Cited by 32 publications

References 41 publications

Temperature-Compensated dB-linear Digitally Controlled Variable Gain Amplifier With DC Offset Cancellation

Temperature-Compensated dB-linear Digitally Controlled Variable Gain Amplifier With DC Offset Cancellation

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm

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