A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm

Abstract

Purpose The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE). Design/methodology/approach The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity. Findings For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc. Originality/value In this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

A State-of-the-Art Review on CMOS Radio Frequency Power Amplifiers for Wireless Communication Systems

“…S. Mariappan et al (2021) presented a dual-stage CMOS PA with adaptive biasing in which the gate voltage of the driver amplifier was adaptively tuned to be in opposition to the third-order transconductance response compared to the main PA [ 148 ]. The biasing voltage was supplied through a current-mirror configured biasing circuit.…”

“… Linear PAE across linear output power for the proposed linearity enhancement techniques [ 116 , 118 , 119 , 121 , 123 , 124 , 129 , 132 , 133 , 134 , 135 , 136 , 137 , 142 , 143 , 144 , 145 , 146 , 147 , 148 , 149 , 150 ]. …”

“…Figure 25. Linear PAE across linear output power for the proposed linearity enhancement techniques[116,118,119,121,123,124,129,[132][133][134][135][136][137][142][143][144][145][146][147][148][149][150].…”