A CMOS image sensor with a simple fixed-pattern-noise-reduction technology and a hole accumulation diode

Yonemoto, Kazuya; Sumi, Hirofumi

doi:10.1109/4.890320

Cited by 65 publications

(26 citation statements)

References 7 publications

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“…있다 [3][4][5][6]. 또한, 이미지 센서에서 동작 범위 향상은 얻을 수 있 는 정보의 양을 확장시키고, 이를 통해 많은 응용분야에 적용 하고 있다 [7][8][9][10][11].…”

Section: 서 론unclassified

Dynamic Range Extension of CMOS Image Sensor with Column Capacitor and Feedback Structure

Lee¹,

Jo²,

Bae³

et al. 2015

Journal of Sensor Science and Technology

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This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using 0.18ìm 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS. Received : Mar. 16, 2015, Revised : Mar. 26, 2015, Apr. 01, 2015, Accepted : Apr. 06, 2015 This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License(http://creativecommons.org/ licenses/bync/3.0) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Section: 서 론unclassified

Dynamic Range Extension of CMOS Image Sensor with Column Capacitor and Feedback Structure

Lee¹,

Jo²,

Bae³

et al. 2015

Journal of Sensor Science and Technology

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“…However, many types of photodetectors have been developed for image sensors, including the bipolar junction transistor (BJT), hole accumulation diodes (HADs), silicon-on-insulator (SOI), and avalanche photodiode (APD). (4)(5)(6) Compared with these photodetectors, the gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector implemented in this study is suitable for the CIS in the case of high-speed binary operation because it is highly sensitive, occupies a small area of the APS, and features effective on-chip integration.…”

Section: Introductionmentioning

confidence: 99%

Complementary Metal Oxide Semiconductor Image Sensor Using a Gate/Body-Tied P-Channel Metal Oxide Semiconductor Field Effect Transistor-Type Photodetector for High-Speed Binary Operation

2018

Sensors and Materials

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In this paper, we propose a CMOS image sensor that uses a gate/body-tied p-chnnel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector for highspeed binary operation. The sensitivity of the gate/body-tied PMOSFET-type photodetector is approximately six times that of the p-n junction photodetector for the same area. Thus, an active pixel sensor with a highly sensitive gate/body-tied PMOSFET-type photodetector is more appropriate for high-speed binary operation. Moreover, the CMOS image sensor for binary operation has the advantages of low power consumption and a simple circuit because an analogto-digital converter is not necessary. The proposed image sensor was fabricated and measured using a CMOS 0.35 μm conventional process.

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“…Finally, the conclusion and directions for future work are provided in Section V. The image sensor is composed of a pixel array, two side column parallel readout circuits, and digital control blocks. The pixel array is based on the 4T two-shared pinned-photodiode [11,14] with a pixel pitch of 2.25 µm.…”

Section: Introductionmentioning

confidence: 99%

“…There are two methods to implement CDS: analog CDS [8][9][10][11][12][13][14][15][16] and digital CDS [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

Cho¹,

Kim²,

Song³

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a 320 × 240 pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung 0.13 µm 1P4M CMOS process and used a 4T APS with a pixel pitch of 2.25 µm. The measured column fixed pattern noise (FPN) is 0.10 LSB.

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A CMOS image sensor with a simple fixed-pattern-noise-reduction technology and a hole accumulation diode

Cited by 65 publications

References 7 publications

Dynamic Range Extension of CMOS Image Sensor with Column Capacitor and Feedback Structure

Dynamic Range Extension of CMOS Image Sensor with Column Capacitor and Feedback Structure

Complementary Metal Oxide Semiconductor Image Sensor Using a Gate/Body-Tied P-Channel Metal Oxide Semiconductor Field Effect Transistor-Type Photodetector for High-Speed Binary Operation

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

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