A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

Abstract

Abstract-In this paper, a 320 × 240 pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung 0.13 µm 1P4M CMOS process and used a 4T APS with a pixel pitch of 2.25 µm. The measured column fixed pattern noise (FPN) is 0.10 LSB.

A High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier

“…In order to verify the performance of the proposed digital CDS in terms of operating speed, a few conventional CDSs are analyzed with the theory described in [ 19 ]. Figure 5 shows the timing diagram for both the conventional CDSs and the proposed digital CDS, assuming a 10-bit single-slope ADC is used.…”

“…It is very well known that it is difficult to obtain a high quality image beyond 8-bit with only an analog CDS. In order to improve the image quality of the analog CDS alone, a dual CDS (analog reset + digital pixel) shown in Figure 5 b is discussed in [ 19 ]. By the addition of only 32 clocks for the analog reset, a high quality image beyond 10-bit is obtained with the dual CDS.…”

“…Table 1 shows the comparison of each CDS. Based on the Samsung 0.13 μm CIS technology, accuracy, readout time, column layout area, and power consumption are analyzed [ 19 ]. From the layout drawing, the column layout of dual CDS is smaller than that of other digital ones, because the digital block is much simpler.…”

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

“…However, the A-CDS has a lot of circuit noises generated from device mismatch, clock feed through error, and charge injection [9]. In this paper, a hybrid correlated double sampling (H-CDS) is discussed to reduce the circuit noises.…”

“…Thus it is hard to use SS-ADC at the high speed systems like HDTV and high resolution cameras to request a frame rate of 30 frames/s or more at a high resolution. In order to overcome the disadvantage of SS-ADC, many approaches have been reported [5][6][7][8][9]. Among them, cyclic ADC or Successive Approximation Register(SAR) ADC are well-known technique for the high frame rate CIS.…”