A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras

Kawahito, Shoji; Yoshida, Mitsuhiro; Sasaki, Masahiro; Umehara, Keijiro; Miyazaki, Daisuke; Tadokoro, Yoshiaki; Murata, Kenji; Doushou, Shirou; Matsuzawa, Akira

doi:10.1109/4.643661

Cited by 113 publications

(21 citation statements)

References 10 publications

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“…The highest efficiency is achieved by sensors that utilize data redundancy within the sensor array (focal-plane compression), whereby compression is performed during the image acquisition process. An exhaustive research in exploiting spatial-redundancy of images developed a variety of CMOS image sensors that perform different focal-plane algorithms such as predictive coding [3], [4], discrete-cosine transform [5], [6], waveletbased processing [7], [8], SPIHT algorithm [9], FBAR and QTD processing [10], and compressive acquisition or compressive sensing [11], [12]. The most promising concepts for exploiting temporal redundancy are mainly biologically inspired (e.g.…”

Section: Introductionmentioning

confidence: 99%

CMOS-integrated photodetectors for neuromorphic and smart imaging applications: A low-cost design and measurement method

Katic

Schmid

Leblebici

2014

IEEE SENSORS 2014 Proceedings

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Several on-chip photodetecting device structures are designed using a low-cost standard 0.18µm CMOS process. The comparison in terms of measured light responsivity and the response speed is presented between conventional and combshaped Nwell-Psubstrate photodiodes, conventional and combshaped, vertical and lateral bipolar-junction phototransistors and a Darlington pair of bipolar-junction phototransistors. The photodetectors are embedded in a conventional three transistor active pixel topology and measured using a customized low-cost measurement setup. The presented comparative study targets neuromorphic and smart imaging applications where the pixel light responsivity and the response speed are crucial performance merits. The study demonstrates the benefits of using standard-CMOS-compatible bipolar-junction structures in these applications. Therefore, the pixel responsivity and response speed are measured for each structure and the results are presented in detail.

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Section: Introductionmentioning

confidence: 99%

CMOS-integrated photodetectors for neuromorphic and smart imaging applications: A low-cost design and measurement method

Katic

Schmid

Leblebici

2014

IEEE SENSORS 2014 Proceedings

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“…Transformation changes the domain of analysis from spatial domain to frequency domain in the case of discrete cosine transform DCT [2], or to wavelet domain in the case of discrete wavelet transform DWT [3] [5]. Most of the information is contained in the low frequency coefficients for DCT or the high level ones for DWT.…”

Section: A Decorrelation Schemesmentioning

confidence: 99%

A comparative study of on chip decorrelation schemes for low power, high resolution infrared sensors

Thabuis

Villard

Belleville

et al. 2009

2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference

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This paper discusses in-sensor decorrelation schemes for infrared applications. These applications require high image quality and low power consumption. Different scenarios involving analog and digital Haar discrete wavelet transform implementations are compared to classical quantization. High level modeling of image sensor shows that a simple decorrelation scheme can reduce column level power consumption while keeping high image quality.I.

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“…In the work [1], a 2D analog Discrete Cosine Transform (DCT) processor and an analog-to-digital converter (ADC) are implemented along with a 128 × 128 pixel array. These two building blocks are the preliminary steps in JPEG compression standard.…”

Section: Introductionmentioning

confidence: 99%

VPIC-based image compression technique for sensor network applications

Wang

Bermak

Boussaid

2011

2011 3rd Asia Symposium on Quality Electronic Design (ASQED)

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This paper examines the implementation considerations of visual pattern image coding (VPIC) algorithm for image compression on the focal plane. Several basic visual patterns that exploit the psychovisual redundancy are adopted in the VPIC coding. These patterns are essentially the same edge patterns developed in classified vector quantization (CVQ). The isometry operation is introduced to help eliminate the gradient angle and edge polarity calculation by exhaustive pattern search. By implementing the time-to-first spike (TFS) digital pixel together with the VPIC coding, the feature that TFS pixels are naturally sorted could be exploited to facilitate and simplify the block mean and gradient magnitude calculation. The reconstructed image quality in terms of Peak Signal-to-Noise Ratio (PSNR) for lena image at the 0.875 bpp could be around 29 dB. This technique is very suitable for Wireless Sensor Network (WSN) applications where image quality is not the primary concern.978-1-4577-0144-3/11/$26.00

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A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras

Cited by 113 publications

References 10 publications

CMOS-integrated photodetectors for neuromorphic and smart imaging applications: A low-cost design and measurement method

CMOS-integrated photodetectors for neuromorphic and smart imaging applications: A low-cost design and measurement method

A comparative study of on chip decorrelation schemes for low power, high resolution infrared sensors

VPIC-based image compression technique for sensor network applications

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