A CMOS Harmonic Rejection Mixer With Mismatch Calibration Circuitry for Digital TV Tuner Applications

Cha, Hyouk-Kyu; Song, Seong-Sik; Kim, Hong-Teuk; Lee, Kwyro

doi:10.1109/lmwc.2008.2002463

Cited by 33 publications

(13 citation statements)

References 4 publications

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“…There are two outstanding parameters of this work, i.e., linearity and harmonic rejection. Comparing all work including an LNA, [2], [4], and [33] shows an IIP3 around dBm while this work shows an IIP3 of dBm and a competitive NF. The OB IIP3 of our work is even higher dBm , but we did not find a good way to benchmark it.…”

Section: G Performance Summary and Benchmarkmentioning

confidence: 63%

Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

Moseley

Klumperink

et al. 2009

IEEE J. Solid-State Circuits

269

209

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A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative "iterative" harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS.Measurements show 34 dB gain, 4 dB NF, and +3 5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order 60 dB over 40 chips, while the digital AIC technique achieves 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.Index Terms-Adaptive interference cancellation, adaptive signal processing, baseband processing, blocker, blocker filtering, CMOS, cross-correlation, digitally assisted, digitally enhanced, harmonic mixing, harmonic rejection, interference mitigation, linearity, LMS, low-noise amplifier (LNA), low-noise transconductance amplifier (LNTA), mismatch, multiphase, multiphase clock, nonlinearity, out-of-band interference, passive mixer, polyphase, receiver, robust receiver, SAW-less, software radio (SWR), software-defined radio (SDR), switching mixer, wideband receiver. A. Out-of-Band NonlinearityNonlinearity may generate intermodulation and harmonic distortion falling on top of the desired signal, or may desensitize a receiver due to blockers and produce cross modulation [10]. Without sufficient RF band-selection filtering, the out-of-band linearity can become the bottleneck since OBI is much stronger than IBI. A wideband LNA as used in [1] and [2] amplifies the desired signal and undesired wideband interference with equal 0018-9200/$26.00

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Section: G Performance Summary and Benchmarkmentioning

confidence: 63%

Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

Moseley

Klumperink

et al. 2009

IEEE J. Solid-State Circuits

269

209

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“…Efficient signal processing algorithms and implementations are crucial for both static and dynamic estimation, calibration and compensation of such transceivers. This is especially challenging for emerging transceivers that have multiple duplicated signal paths on chip (for MIMO communication [19], beamforming [18], harmonics rejection [3], nonlinearity cancellation [9] etc.). With deeply scaled technology, devices in different signal paths will differ a lot from each other, so that tuning and compensation signal processing will be crucial.…”

Section: Parameter Estimation and Calibration In Reconfigurable Transmentioning

confidence: 99%

“…Multi-path mixing is a promising solution to handle oddorder harmonic mixing [3]. In this approach, the outputs of multiple switching mixers are combined, each weighted with an appropriate weighting factor to approximate the aggregate LO as a pseudo-sinusoid signal (Fig.2).…”

Section: Wide Band Transceivers With Harmonic Rejectionmentioning

confidence: 99%

Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited)

Min

Khalaf

et al. 2013

SiPS 2013 Proceedings

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Mainstream foundries are leaping toward 14nm node and beyond. Although aggressive scaling can substantially improve digital circuit, it is very controversial for analog circuit. However, analog circuit still has to follow the scaling trend because a single chip integration offers key commercial advantages. To optimally achieve the best performance/power/cost tradeoff with deeply scaled technology nodes, there is a clear trend and paradigm shift towards digital intensive and digitally assisted transceivers. Successes of such transceivers have been proven for individual transceiver components and narrow band systems. When targeting emerging communication standards, higher carrier frequencies, further technology scaling and reconfigurable radios, required signal processing design and implementation are orders of magnitudes more challenging but potential gains are promising. Illustrated with a variety of transceivers representing emerging architectures designed for different sub-6Ghz and 60Ghz communication systems, we will depict key challenges that we experienced in our design and optimization process with 40nm and 28nm technology nodes. 324 2013 IEEE Workshop on Signal Processing Systems 978-1-4673-6238-2/13 $31.00

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“…For example, in an envelope detector [6], analog-to-digital converter (ADC), and digital signal processor is used for the calibration. In [7][8][9][10][11][12][13] in addition, it puts forward the evaluation of the output spectrum of the envelope detector output connected to reduce the extraction of the third order distortion, which requires a single chip implementation of FFT engine.…”

Section: Introductionmentioning

confidence: 99%

Research on the Optimization and Ascension of Target Accuracy for RF Systems

Liu¹

2015

Proceedings of the 2015 International Conference on Electrical, Computer Engineering and Electronics

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Abstract.A digital built-in calibration (BIC) system is presented to automatically adjust the linearity performance of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. In this paper, we conduct research on optimization and ascension of target accuracy for RF systems. To minimize the area and power overhead of the system, an envelope detector was employed to reduce the speed of operation for the ADC and digital blocks, and an efficient IM3 estimation method has been developed. Closed-loop simulations of this calibration system and a low-noise amplifier with digitally-tunable third-order linearity performance showed the feasibility of the synthesized digital blocks in standard CMOS technology. The experimental result proves the effectiveness of proposed method.

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A CMOS Harmonic Rejection Mixer With Mismatch Calibration Circuitry for Digital TV Tuner Applications

Cited by 33 publications

References 4 publications

Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited)

Research on the Optimization and Ascension of Target Accuracy for RF Systems

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