For space applications, high performance and codes are a very suitable fault tolerant technique to satisfy high reliability are two indicators that become more and the error detecting requirements at a low cost. In the end, an more important to a processor. After an analysis of the implemental result of CORDIC processor for special space different architectures and fault tolerant techniques, an applications is given. implementation of CORDIC processor employing 3N codes for error detection in a 3 granularly pipelined II. THE CORDIC ALGORITHM architecture is presented. A high data throughput of The original CORDIC algorithm is a bit-iterative 300MFLOPS is achieved and the circuit complexity only implementation of the forward and backward Givens increased 9.5% after applied the fault tolerant rotation, also called rotation and vectoring, respectively. technique. The unified CORDIC algorithm [2] is defined by Fxi+± xi vM7i 2-s(mi) Yi I.