A CMOS direct access arrangement using digital capacitive isolation

Krone, Andy; Tuttle, T.; Scott, J. F.; Hein, J.P.; Dupuis, T.; Sooch, N.

doi:10.1109/isscc.2001.912647

Cited by 19 publications

(8 citation statements)

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“…Experimental measurements were carried out at 3.3-V voltage supply up to a data rate of 40 Mbit/s and confirmed the simulated performance. (5) 3.8/0.9 (6) Assembling/Package Standard Stacked chips with DAF (7) Standard Standard Standard…”

Section: Resultsmentioning

confidence: 99%

“…An integrated galvanic barrier can be implemented by using silicon dioxide (SiO 2 ), which exhibits a breakdown voltage (BV) of about 1000 V/µm [3], sometimes in combination with silicon nitride (Si 3 N 4 ) and oxynitride (SiON) to further improve its isolation rating [4]. Oxide galvanic isolation has been successfully exploited in recent years for highly integrated isolated data [5][6][7] and power transfer interfaces [8][9][10][11][12] by means of on-chip capacitors or stacked transformers. However, oxide insulation can reliably provide a limited surge capability (typically 5-6 kV), since increasing the oxide thickness produces wafer mechanical stress and second order BV effects.…”

Section: Technologies For Chip-scale Galvanic Isolatorsmentioning

confidence: 99%

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A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

et al. 2020

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This paper exploits an effective approach to overcome the breakdown limitations of traditional galvanic isolators based on chip-scale isolation barriers, thus achieving a very high isolation rating (i.e., compliant with the reinforced isolation requirements). Such an approach is based on radio frequency (RF) planar coupling between two side-by-side co-packaged chips. Standard packaging along with proper assembling techniques can be profitably used to go beyond 20-kV surge voltage without using expensive or exotic isolation components. As a proof of concept, a bidirectional data transfer system based on RF planar coupling able to withstand an isolation rating as high as 25 kV has been designed in a low-cost standard 0.35-µm CMOS technology. Experimental measurements demonstrated a maximum data rate of 40 Mbit/s using a carrier frequency of about 1 GHz. The adopted approach also guarantees a common mode transient immunity (CMTI) of 250 kV/µs, which is a first-rate performance in view of next generation galvanic isolators for wide-bandgap power semiconductor devices, such as gallium nitride high-electron mobility transistors (GaN HEMTs) and silicon carbide (SiC) MOSFETs.

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Section: Resultsmentioning

confidence: 99%

Section: Technologies For Chip-scale Galvanic Isolatorsmentioning

confidence: 99%

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

et al. 2020

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“…However, optocouplers suffer from a limited operational temperature range, due to the decrease in output power of the VCSEL/LED and the increase in dark currents in the photodiode at higher temperatures [2]. Other galvanically isolated topologies, such as magnetic and capacitive coupled isolators [1], [3]- [6] overcome the temperature issue but suffer from limited isolation capability, as their link efficiency is greatly dependent on the isolation distance.…”

Section: Introductionmentioning

confidence: 99%

A Flexible Low-Latency DC-to-4 Gbit/s Link Operating from −40 to +200°C in 28nm CMOS for Galvanically Isolated Applications

Ooms

Reynaert

2018

2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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This paper presents a communication link for galvanically isolated (GI) applications. The proposed link employs a 120 GHz OOK transmitter and receiver with a PTFE fiber as directive channel to reduce transmission losses. The receiver is implemented with a replica temperature compensation loop to provide operation from −40 to +200 • C and thereby overcome the limitations of existing optical and magnetically coupled solutions. The presented work reports an isolated communication link with a data rate of 4 Gbit/s and reports the lowest latency of 1 ns with less than 4.5% variation over the entire measured temperature range. The power consumption of the entire link is only 52.4 mW and achieves 13.1 pJ/bit efficiency.

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“…There are many examples reported about DTI. [8][9][10][11][12][13][14][15][16][17]28) SOI technology is also shown to be effective for isolation in the vertical direction. [18][19][20][21][22][23][24][25][26][27] In this work, we introduce the unified impedance model to analyze the breakdown voltage of various isolation structures.…”

Section: Introductionmentioning

confidence: 99%

Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

Takeuchi¹,

Kuroda²,

Sugawa³

2015

Jpn. J. Appl. Phys.

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We analyzed the shared voltages of multiple trench gaps on a silicon-on-insulator (SOI) substrate and showed the conditions for improving the breakdown voltage surrounded by these isolated structures. We introduced a unified impedance model instead of the capacitive model of trench gaps and determined the effective conditions for improving the breakdown voltage. The first condition is to reduce the impedance of trench gaps. In this case, the leak current gives a low limit of trench gap resistance. The second condition is to increase the substrate resistance. As silicon substrate resistance is not very high, this condition is not useful for the silicon substrate, but for other materials such as ceramics. We confirmed the effectiveness of these conditions from the simulation and experimental results of a fabricated chip.

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A CMOS direct access arrangement using digital capacitive isolation

Cited by 19 publications

References 0 publications

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

A Flexible Low-Latency DC-to-4 Gbit/s Link Operating from −40 to +200°C in 28nm CMOS for Galvanically Isolated Applications

Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

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