A CMOS Current Steering Neurostimulation Array With Integrated DAC Calibration and Charge Balancing

Abstract

An 8-channel current steerable, multi-phasic neural stimulator with on-chip current DAC calibration and residue nulling for precise charge balancing is presented. Each channel consists of two sub-binary radix DACs followed by wide-swing, high output impedance current buffers providing time-multiplexed source and sink outputs for anodic and cathodic stimulation. A single integrator is shared among channels and serves to calibrate DAC coefficients and to closely match the anodic and cathodic stimulation phases. Following calibration, the differential non-linearity is within ± 0.3 LSB at 8-bit resolution, and the two stimulation phases are matched within 0.3%. Individual control in digital programming of stimulation coefficients across the array allows altering the spatial profile of current stimulation for selection of stimulation targets by current steering. Combined with the self-calibration and current matching functions, the current steering capabilities integrated on-chip support use in fully implanted neural interfaces with autonomous operation for and adaptive stimulation under variations in electrode and tissue conditions. As a proof-of-concept we applied current steering stimulation through a multi-channel cuff electrode on the sciatic nerve of a rat.

A Programmable EEG Monitoring SoC with Optical and Electrical Stimulation for Epilepsy Control

“…12 illustrates the block diagram of the stimulator, which is composed of a stimulation controller, an 8-bit current- steering digital-to-analog converter (DAC) with switches for current direction control and a range of 0-510 µA, and an optical stimulation module constructed by discrete components. The electrical stimulation method is similar to an Hbridge structure, which is featured on simple to realize and well phase match for charge-balanced stimulus [44], by using the digital circuit to control the switch on the output stage of current DAC. The comment, which is decoded by the arithmetic logic unit with a simple check at the first stage, is set to activate the stimulator at the beginning.…”

An ASIC for Recording and Stimulation in Stacked Microchannel Neural Interfaces

“…In this work charge error has been reduced to < 2% with no active discharge mechanism by adjusting command timing. Charge balancing can be achieved using a capacitor in series with I S , switched to charge on the first phase and discharge on the second phase, the current in the second phase being cut-off when the charge reaches zero or an active charge balancing arrangement to achieve < 1% error [49], [50].…”

On the DC Offset Current Generated during Biphasic Stimulation: Experimental Study

“…In a practical case, the electrode matrix is made of tens of multiple hexagonal stimulation sites alternately activated that share the same return electrode [12][13][14][15][16][17][18]. Figure 8, representing two hexagonal stimulation sites HEXa and HEXb that are simultaneously active and share the same return electrode.…”

“…The charge during the opposite phases of sourcing and sinking currents should be balanced, as well as the impedance of the electrodes needs to be perfectly matched. For this purpose, several techniques and stimulation strategies for a precise charge balancing have been proposed at the IC level to minimize the undesired DC offset current generated by the biphasic stimulation [12][13][14][15][16][17][18].…”

“…Based on the weakness of the signal to monitor (tens of nanoamperes), the DC offset current value in the literature usually refers to CAD simulation or measurements where the electrodes and the tissues are substituted with an equivalent quasi-static loss electric model constituted by passive components (resistor in series with a parallel capacitor and resistor). Moreover, such a DC offset current value reported in the literature relates to a defined stimulation pattern and a specific set of electrical parameters of the biphasic signal [12][13][14][15][16][17][18].…”